Maxim DS80C400, Руководство пользователя, Страница: 47 / 96

DS80C400 Network Microcontroller
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Table 9. Data Memory Cycle Stretch Values
APPROXIMATE
RD
,
WR
PULSE WIDTH
(IN OSCILLATOR CLOCKS)
MD2 MD1 MD0
STRETCH
VALUE
MOVX
MACHINE
CYCLES
(4X/
2X
= 1
CD1:0 = 00)
(4X/
2X
= 0
CD1:0 = 00)
(4X/
2X
= X
CD1:0 = 10)
(4X/
2X
= X
CD1:0 = 11)
0 0 0 0 (Note 1) 2 0.5 t
CLK
1 t
CLK
2 t
CLK
512 t
CLK
0 0 1 1 (Note 2) 3 1 t
CLK
2 t
CLK
4 t
CLK
1024 t
CLK
0 1 0 2 4 2 t
CLK
4 t
CLK
8 t
CLK
2048 t
CLK
0 1 1 3 5 3 t
CLK
6 t
CLK
12 t
CLK
3072 t
CLK
1 0 0 4 9 4 t
CLK
8 t
CLK
16 t
CLK
4096 t
CLK
1 0 1 5 10 5 t
CLK
10 t
CLK
20 t
CLK
5120 t
CLK
1 1 0 6 11 6 t
CLK
12 t
CLK
24 t
CLK
6144 t
CLK
1 1 1 7 12 7 t
CLK
14 t
CLK
28 t
CLK
7168 t
CLK
Note 1: All internal MOVX operations execute at the 0 stretch setting.
Note 2: Default stretch setting for external MOVX operations following reset.
Internal MOVX SRAM
The DS80C400 contains 9kB of SRAM that is physically divided into a 1kB block and an 8kB block. The 1kB block
can be used to support the extended stack-pointer function or can be used as general-purpose MOVX data
memory. The 8kB block is used by the Ethernet MAC as frame-buffer memory for incoming or outgoing packet data
and can, at the same time, be accessed by the DS80C400 as MOVX data memory. While the MAC is in use,
special care should be taken by user software to prevent undesirable MOVX writes from corrupting frame-buffer
memory. The address mapping of the 1kB block and the 8kB block are governed by the internal data-memory
configuration bits (IDM1, IDM0) in the memory control register (MCON;C6h). Note that when the SA bit (ACON.2)
is set, 1kB of the MOVX data memory is accessed by the 10-bit expanded stack pointer. Changing the IDM1:0
configuration bits while SA = 1 does not disrupt the extended stack-pointer function. Internal MOVX memory
accesses do not generate
WR
or
RD
strobes.
The DS80C400 contains an additional 256 Bytes of internal SRAM that is used to configure and operate the 15
CAN-controller message centers. The address location of this 256-Byte block is determined by the CAN data-
memory assignment bit (CMA) in the memory control register (MCON; C6h).
Table 10. Internal MOVX SRAM Configuration
IDM1 IDM0 CMA
8kB BLOCK
(MAC/MOVX DATA)
1kB BLOCK
(STACK/MOVX DATA)
256-BYTE
(CAN DATA MEMORY)
0 0 0 00E000h–00FFFFh 00DC00h–00DFFFh 00DB00h–00DBFFh
0 0 1 00E000h–00FFFFh 00DC00h–00DFFFh FFDB00h–FFDBFFh
0 1 0 000000h–001FFFh 002000h–0023FFh 00DB00h–00DBFFh
0 1 1 000000h–001FFFh 002000h–0023FFh FFDB00h–FFDBFFh
1 0 0 FFE000h–FFFFFFh FFDC00h–FFDFFFh 00DB00h–00DBFFh
1 0 1 FFE000h–FFFFFFh FFDC00h–FFDFFFh FFDB00h–FFDBFFh
Extended Stack Pointer
The DS80C400 supports both the traditional 8-bit and an extended 10-bit stack pointer that improves the
performance of large programs written in high-level languages such as C. To enable the 10-bit stack pointer, set
the stack-address mode bit, SA (ACON.2). The bit is cleared following a reset, forcing the device to use an 8-bit
stack located in the scratchpad RAM area. When the SA bit is set, the device addresses up to 1kB of internal
MOVX memory for stack purposes. The 10-bit stack pointer address is generated by concatenating the lower two
bits of the extended stack pointer (ESP;9Bh) and the traditional 8051 stack pointer (SP;81h).
On-Chip Arithmetic Accelerator
An on-chip math accelerator allows the microcontroller to perform 32-bit and 16-bit multiplication, division, shifting,
and normalization using dedicated hardware. Math operations are performed by sequentially loading three special
registers. The mathematical operation is determined by the sequence in which three dedicated SFRs (MA, MB, and
MCNT0) are accessed, eliminating the need for a special step to choose the operation. The normalize function