Maxim DS80C400, Руководство пользователя, Страница: 13 / 96

DS80C400 Network Microcontroller
13 of 96
ELECTRICAL CHARACTERISTICS (NONMULTIPLEXED ADDRESS/DATA BUS)
(Note 1)
(V
CC3
= 3.0V to 3.6V, V
CC1
= 1.8V ±10%, T
A
= -40°C to +85°C.)
75MHz VARIABLE CLOCK
PARAMETER SYMBOL
MIN MAX MIN MAX
UNITS
External Crystal Frequency 4 40
Clock Mutliplier 2X Mode 16 37.5
Clock Multiplier 4X Mode
1 / t
CLK
11 18.75
MHz
External Oscillator Frequency DC 75
Clock Mutliplier 2X Mode 16 37.5
Clock Multiplier 4X Mode
1 / t
CLK
11 18.75
MHz
PSEN
Pulse Width t
PLPH
21.7 2t
CLCL
- 5 ns
PSEN
Low to Valid Instruction In t
PLIV
9.7 2t
CLCL
- 17 ns
Input Instruction Hold After
PSEN
t
PXIX
0 0 ns
Input Instruction Float After
PSEN
t
PXIZ
See MOVX
Characteristics
ns
Port 7 Address to Valid Instruction In t
AVIV1
21.0 3t
CLCL
- 19 ns
Port 2, 4, 6 Address or Port 4 CE to Valid
Instruction In
t
AVIV2
27.7 3t
CLCL
+ t
CLCH
- 19 ns
Note 1: Specifications to -40°C are guaranteed by design and not production tested.
Note 2: All parameters apply to both commercial and industrial temperature operation, unless otherwise noted.
Note 3: t
CLCL
, t
CLCH
, t
CHCL
are time periods associated with the internal system clock and are related to the external clock (t
CLK
) as defined in the
the System Clock Time Periods table.
Note 4: The precalculated 75MHz min/max timing specifications assume an exact 50% duty cycle.
Note 5: All signals characterized with load capacitance of 80pF except Port 0, Port 2, ALE, PSEN , RD, and WR with 100pF. The following
signals, when configured for memory interface, are also characterized with 100pF loading: Port 4 (
CE0-3
, A16–A19), Port 5.4–5.7
(
PCE0-3
), Port 6.0–6.5 (
CE4-7
, A20, A21), Port 7 (demultiplexed mode A0–A7).
Note 6: References to the XTAL, XTAL1, or CLK signal in timing diagrams is to assist in determining the relative occurrence of events, not for
determing absolute signal timing with respect to the external clock.