Maxim DS80C400, Руководство пользователя, Страница: 14 / 96

DS80C400 Network Microcontroller
14 of 96
MOVX CHARACTERISTICS (NONMULTIPLEXED ADDRESS/DATA BUS) (Note 1)
(V
CC3
= 3.0V to 3.6V, V
CC1
= 1.8V +±10%, T
A
= -40°C to +85°C.)
PARAMETER SYMBOL MIN MAX UNITS
STRETCH
VALUES
C
ST
(MD2:0)
2t
CLCL
- 5 C
ST
= 0
3t
CLCL
- 5
1
£
C
ST
£
3
Input Instruction Float After
PSEN
t
PXIZ
11t
CLCL
- 5
ns
4 £ C
ST
£ 7
PSEN
High to Data Address, Port 4 CE,
Port 5 PCE Valid
t
PHAV
t
CHCL
- 3 ns
2t
CLCL
- 5 C
ST
=0
RD
Pulse Width (P3.7 or
PSEN
) t
RLRH
(4 x C
ST
) t
CLCL
- 3
ns
1 £ C
ST
£ 7
2t
CLCL
- 5 C
ST
=0
WR
Pulse Width (P3.6)
t
WLWH
(4 x C
ST
)t
CLCL
- 3
ns
1
£
C
ST
£
7
2t
CLCL
- 17 C
ST
= 0
RD
(P3.7 or
PSEN
) Low to Valid Data In t
RLDV
(4 x C
ST
)t
CLCL
- 17
ns
1 £ C
ST
£ 7
Data Hold After
RD
(P3.7 or
PSEN
) High t
RHDX
-2 ns
t
CLCL
- 5 C
ST
= 0
2t
CLCL
- 5
1
£
C
ST
£
3
Data Float After
RD
(P3.7 or
PSEN
) High t
RHDZ
6t
CLCL
- 5
ns
4 £ C
ST
£ 7
2t
CLCL
- 3 C
ST
= 0
3t
CLCL
- 3
1
£
C
ST
£
3
PSEN
High to
WR
Low t
PHWL
11t
CLCL
- 3
ns
4 £ C
ST
£ 7
2t
CLCL
- 3 C
ST
= 0
3t
CLCL
- 3
1
£
C
ST
£
3
PSEN
High to (
RD
or
PSEN
) Low t
PHRL
11t
CLCL
- 3
ns
4 £ C
ST
£ 7
3t
CLCL
- 19 C
ST
= 0
(4 x C
ST
+ 2)t
CLCL
- 19
1
£
C
ST
£
3
Port 7 Address to Valid Data In t
AVDV1
(4 x C
ST
+ 10)t
CLCL
-
19
ns
4 £ C
ST
£ 7
3t
CLCL
+ t
CLCH
- 19 C
ST
= 0
(4 x C
ST
+ 2)t
CLCL
+
t
CLCH
- 19
1 £ C
ST
£ 3
Port 2, 4, 6 Address, Port 4 CE or Port 5
PCE to Valid Data In
t
AVDV2
(4 x C
ST
+ 10)t
CLCL
+
t
CLCH
- 19
ns
4 £ C
ST
£ 7
t
CLCL
- 5 C
ST
= 0
2t
CLCL
- 5 1
£
C
ST
£
3
Port 7 Address to (
RD
or
PSEN
) or
WR
Low
t
AVWL1
10t
CLCL
- 5
ns
4
£
C
ST
£
7
t
CLCL
+ t
CLCH
- 5 C
ST
= 0
2t
CLCL
+ t
CLCH
- 5 1
£
C
ST
£
3
Port 2, 4, 6 Address, Port 4 CE or Port 5
PCE to (
RD
or
PSEN
) or
WR
Low
t
AVWL2
10t
CLCL
+ t
CLCH
- 5
ns
4
£
C
ST
£
7
Data Valid to
WR
Transition t
QVWX
0 ns
t
CLCL
- 4 C
ST
= 0
2
CLCL
- 7 1 £ C
ST
£ 3 Data Hold After
WR
High t
WHQX
6t
CLCL
- 7
ns
4
£
C
ST
£
7
t
CHCL
- 5 t
CHCL
+ 13 C
ST
= 0
t
CLCL
+ t
CHCL
- 5 t
CLCL
+ t
CHCL
+12 1 £ C
ST
£ 3
(
RD
or
PSEN)
or
WR
High to Port 4 CE
or Port 5 PCE High
t
WHCEH
5t
CLCL
+ t
CHCL
-5 5t
CLCL
+ t
CHCL
+12
ns
4
£
C
ST
£
7
Note 1: Specifications to -40°C are guaranteed by design and not production tested.
Note 2: All parameters apply to both commercial and industrial temperature operation unless otherwise noted.
Note 3: CST is the stretch cycle value as determined by the MD2, MD1, and MD0 bits of the CKCON register. t
CLCL
, t
CLCH
, t
CHCL
are time periods
associated with the internal system clock and are related to the external clock. See the System Clock Time Periods table.
Note 4: All signals characterized with load capacitance of 80pF except Port 0, Port 2, ALE, PSEN , RD , and WR with 100pF. The following
signals, when configured for memory interface, are also characterized with 100pF loading: Port 4 (
CE0-3
, A16–A19), Port 5.4–5.7
(
PCE0-3
), Port 6.0–6.5 (
CE4-7
, A20, A2), Port 7 (demultiplexed mode A0–A7).
Note 5: References to the XTAL or CLK signal in timing diagrams is to assist in determining the relative occurrence of events, not for determing
absolute signal timing with respect to the external clock.