LAPIS Semiconductor ML610471, Руководство пользователя, Страница: 93 / 281

ML610471/472/473/Q471/Q472/Q473 User's Manual
Chapter 6 Clock Generation Circuit
6-11
6.4.2 Functioning P20 (LSCLK) as the low-speed clock output
Set P20MD bit (bit0 of P2MOD register) to “1” for specifying the low-speed clock output as the secondary function of
P22.
Register
name
P2MOD register (Address: 0F214H)
Bit 7 6 5 4 3 2 1
0
Bit name
- - - - - - P21MD
P20MD
Setting
value
- - - - - - *
1
Set the P20C1 bit (P2CON1 register bit 0) to "1" and the P20C0 bit (P2CON0 register bit 0) to "1" for selecting the P20
pin state mode to CMOS output.
Register
name
P2CON1 register (Address: 0F213H)
Bit 7 6 5 4 3 2 1
0
Bit name
- - - - - - P21C1
P20C1
Setting
value
- - - - - - *
1
Register
name
P2CON0 register (Address: 0F212H)
Bit 7 6 5 4 3 2 1
0
Bit name
- - - - - - P21C0
P20C0
Setting
value
- - - - - - *
1
Data of P20D bit (bit0 of P2D register) does not affect to the low speed clock output function, so don’t care the data for
the function.
Register
name
P2D register (Address: 0F210H)
Bit 7 6 5 4 3 2 1
0
Bit name
- - - - - - P21D
P20D
Setting
value
- - - - - - *
**
- : Bit that does not exist
* : Bit not related to the low-speed clock function
** : Don’t care
Note:
P20 (Port 2) is an output-only port and does not have the register to select the data direction(input or output).