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ML610471/472/473/Q471/Q472/Q473 User's Manual
Chapter 5 Interrupt
5-16
5.3.4 Notes on Interrupt Routine
Notes are different in programming depending on whether a subroutine is called or not by the program in executing an
interrupt routine, whether multiple interrupts are enabled or disabled, and whether such interrupts are maskable or
non-maskable.
Status A: Maskable interrupt is being processed
A-1: When a subroutine is not called by the program in executing an interrupt routine
A-1-1: When multiple interrupts are disabled
•Processing immediately after the start of interrupt routine execution
No specific notes.
•Processing at the end of interrupt routine execution
Specify the RTI instruction to return the contents of the ELR register to the PC and those of the EPSW
register to PSW.
A-1-2: When multiple interrupts are enabled
•Processing immediately after the start of interrupt routine execution
Specify "PUSH ELR, EPSW" to save the interrupt return address and the PSW status in the stack.
•Processing before the master interrupt enable(MIE) bit is set
Specify “RB Exx” to invalidate the accepted interrupt. (Exx: the accepted interrupt enable flag)
•Processing at the end of interrupt routine execution
Specify “DI” not to execute the same interrupt routine.
Specify “SB Exx” to validate the accepted interrupt. (Exx: the accepted interrupt enable flag)
Specify “POP PC, PSW” instead of the RTI instruction to return the contents of the stack to PC and
PSW.
Example of description:
Status A-1-1 Example of description: Status
A-1-2
Intrpt_A-1-1; ; A-1-1 state Intrpt_A-1-2; ; Start
DI ; Disable interrupt PUSH LR,EPSW
; Save ELR and EPSW at the
beginning
: :
: RB Exx
; Invalidate the accepted interrupt
(*1)
: EI ; Enable interrupt (*2)
RTI ; Return PC from ELR :
; Return PSW form
EPSW
:
; End DI ; Disable interrupt
SB Exx ; Validate the accepted interrupt
POP PC,PSW ; Return PC from the stack
; Return PSW from the stack
; End
(*1) When multiple interrupts are enabled, please set the accepted interrupt enable flag to “0” to prevent
the occurrence of the accepted interrupt.
(*2) After enabling interrupt, not only a higher-priority interrupt than the accepted interrupt but also a
lower-priority interrupt than that occurs.