LAPIS Semiconductor ML610471, Руководство пользователя, Страница: 211 / 281

ML610471/472/473/Q471/Q472/Q473 User's Manual
Chapter 17 RC Oscillation Type A/D Converter
17-6
17.2.4 RC-ADC Mode Register (RADMOD)
Address: 0F308H
Access: R/W
Access size: 8-bit
Initial value: 00H
7 6 5 4 3 2 1 0
RADMOD
RACK2 RACK1 RACK0 RADI OM3 OM2 OM1 OM0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
RADMOD is a special function register (SFR) used to select the A/D conversion mode of the RC-ADC.
[Description of Bits]
•
OM3-0 (bits 3 to 0)
The OM3–0 bits are used to select an oscillation mode for the RC oscillator circuits.
OM3 OM2 OM1 OM0
Description
0 0 0 0
initial value
0 0 0 1
Prohibited
0 0 1 0
Prohibited
0 0 1 1
Prohibited
0 1 0 0
Prohibited
0 1 0 1
RS1–CS1 oscillation mode
0 1 1 0
RT1–CS1 oscillation mode
0 1 1 1
IN1 pin external clock input mode
1 * * *
Prohibited
•
RADI (bit 4)
The RADI bit is used to choose whether to generate the RC-ADC interrupt request signal (RADINT) by an
overflow at Counter A or Counter B.
RADI
Description
0 Generates an interrupt request by Counter A overflow (initial value).
1 Generates an interrupt request by Counter B overflow.
•
RACK2-0 (bits 7 to 5)
The RACK2 to RACK0 bits are used to select the base clock of Counter A (BSCLK).
RACK2 RACK1 RACK0
Description
0 0 0
LSCLK (initial value)
0 0 1
LSCLK×2
0 1 0
HSCLK
0 1 1
1/2HSCLK
1 0 0
1/4HSCLK
1 0 1
1/8HSCLK
1 1 *
Setting prohibited (no clock is supplied)
Note:
When specifying LSCLK x 2 for the base clock, enable the operation of the low-speed double clock by setting bit 2
(ENMLT) of the frequency control register 1 (FCON1) to “1”.