LAPIS Semiconductor ML610471, Руководство пользователя, Страница: 90 / 281

ML610471/472/473/Q471/Q472/Q473 User's Manual
Chapter 6 Clock Generation Circuit
6-8
6.3.2.2 Operation of High-Speed Clock Generation Circuit
The high-speed clock generation circuit allows the start/stop control of oscillation by using the frequency control registers
0 and 1 (FCON0 and FCON1).
Oscillation can be started by setting the ENOSC bit of FCON1 to "1" after selecting a high-speed oscillation frequency
with FCON0. After the start of oscillation, HSCLK starts supply of a clock to the peripheral circuits following the elapse
of the high-speed oscillation start period (T
RC
) and the oscillation stabilization time of the high-speed oscillation clock
(OSCLK).
The high-speed clock generation circuit stops oscillation when it shifts to the STOP mode by software. When the STOP
mode is released by external interrupt, HSCLK supplies clocks to peripheral circuits following the elapse of the
high-speed oscillation start period (T
RC
) and the oscillation stabilization time of the high-speed clock (OSCLK). The
oscillation stabilization time is for 16 clocks.
Figure 6-5 shows the waveforms of the high-speed clock generation circuit.
Figure 6-5 Operation of High-Speed Clock Generation Circuit
High-speed oscillation 16 counts
T
RC
: High-speed oscillation start time
High-speed
oscillation
waveform
High-speed
clock
HSCLK
High-speed clock
oscillation enabled
ENOSC
High-speed oscillation 16 counts
High-speed
oscillation
started
STOP
mode
External
interrupt
occurred
High-speed oscillation waveform
High-speed oscillation waveform
Program restarted time depends
on the SYSCLK bit
HSCLK waveform
Low-speed clock oscillation waveform
T
XTL
: Low-speed oscillation start time
Low-speed clock oscillation waveform
HSCLK waveform
T
RC
: High-speed oscillation start time
High-speed
oscillation
Stop
Low-Speed Clock
oscillation
waveform
Low-speed oscillation 8192 counts