LAPIS Semiconductor ML610471, Руководство пользователя, Страница: 115 / 281

ML610471/472/473/Q471/Q472/Q473 User's Manual
Chapter 9 Timer
9-1
9. Timer
9.1 Overview
This LSI includes 2 channels of 8-bit timers.
For input clocks, see Chapter 6, “Clock Generation Circuit”.
9.1.1 Features
•
The timer interrupt (TMnINT) is generated when the values of timer counter register (TMnC, n=2, 3) and timer
data register (TMnD) coincide.
•
A timer configured by combining timer 2 and timer 3 can be used as a 16-bit timer.
•
For the timer clock, the low-speed clock (LSCLK), high-speed time base clock (HTBCLK), or external clock can
be selected.
•
A 16bit-timer 2 & 3 has clock frequency measurement mode, which can count HTBCLK and generates the
timer interrupt (TM3INT) when the count ends.
Using the count data to know the frequency by software can determine more accurate baud-rate.
9.1.2 Configuration
Figure 9-1 shows the configuration of the timers.
TMnCON0 : Timer control register 0
TMnCON1 : Timer control register 1
TMmD, TMnD : Timer data register
TMmC, TMnC : Timer counter register
(a) In 8-bit Timer Mode (Timers 2, Timer 3)
(b) In 16-bit Timer Mode (Timers 2, Timer 3)
TMnC
Data bus
TMmINT
LSCLK
TMnCON0
TMnCON1
R
Matched
Comparator
HTBCLK
Write TMmC
TnCK
Write TMnC
8
8
8 8
TMnD TMmD TMmC
R
8 8
16
8 8
16
External clock
PP44/T2CK
TMmC latch Read TMnC
n,m = 2,3
TMnC
8
Data bus
TMnINT
LSCLK
TMnCON0
TMnCON1
R
Matched
TMnD
Comparator
8
HTBCLK
8
n=2, 3
Write TMnC
TnCK
8
External clock
P44/T2CK
P45/T3CK