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ML610471/472/473/Q471/Q472/Q473 User's Manual
Appendix E Check List
Appendix E-1
Appendix E Check List
This Check List has notes to prevent commonly-made programming mistakes and frequently overlooked or misunderstood
hardware features of the MCU. Check each note listed up chapter by chapter while coding the program or evaluating it using the
MCU.
Chapter 1 Overview
•About unused pins
[ ] Please confirm how to handle the unused pins(Refer to Section 1.3.4 in the user’s manual).
Chapter 2 CPU and Memory Space
•Program Memory size
[ ] 7,936 Byte (0:0000H to 0:1EFFH)
•Data RAM size
[ ] 512Byte (0:E000H to 0:E1FFH)
•Unused area
[ ] Please fill test area 0:1C00H0:1FFFH with BRK instruction code “0FFH” (Refer to a startup file “ML610471.asm”, “ML610472.asm”,
“ML610473.asm” or programming in the source code).
[ ] For fail safe in your system, please fill unused program memory area (your program code does not use) with BRK instruction code
“0FFH”. We will fill the area with the code “0FFH” at LAPIS Semiconductor’s factory programming.
•RAM initialization
[ ]
The hardware reset does not initialize RAM. Please initialize RAM by the software.
Chapter 3 Reset
•Reset activation pulse width
[ ]
Minimum 200us (Refer to Appendix C-2 in the user's manual)
•Power-on reset occurrence power rise time
[ ]
Maximum 10ms (Refer to Appendix C-2 in the user's manual)
•Reset status flag
[ ]
No flag is provided that indicates the occurrence of reset by the RESET_N pin (Refer to section 3.2.2. in the user's manual).
•BRK instruction reset
[ ] In system reset by the BRK instruction, no special function register (SFR) is initialized either. Therefore initialize the SFRs
by your software (see Section 3.3.1 in the User's Manual).
Chapter 4 MCU Control Function
•STOP mode
[ ] When the MIE flag is "0", the stop code acceptor (STPACP) cannot be enabled under the condition where both the interrupt enable and
request flags become "1"
(Refer to Sections 4.2.2 and 4.2.3. in the user's manual)
.
[ ] Place two NOP instructions next to the instruction that sets the STP bit to "1"
(Refer to Section 4.3.3. in the user's manual).
•HALT mode
[ ] Place two NOP instructions next to the instruction that sets the HLT bit to "1"
(Refer to Section 4.3.2. in the user's manual).
•BLKCON register
[ ] BLKCON registers enable or disable corresponsive each peripheral (Refer to Section 4.2.4 - 4.2.8. in the user’s manual).
[ ]
When certain bits of block control registers are set to “1”, corresponding peripherals are reset (all registers are reset) and
operating clocks for the peripherals stop.
Chapter 5 Interrupts
•Unused interrupt vector table
[ ] Please define all unused interrupt vector tables for fail safe.
•Non-maskable interrupt
[ ] The watchdog timer interrupt (WDTINT) is a non-maskable interrupt that does not depend on MIE flag
(Refer to Sections 5.2.8. and
5.3 in the User's Manual)
.