Keysight Technologies D9020DDRC, Руководство пользователя

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DDR2(+LP) Compliance Testing Methods of Implementation 43
Measurement Clock Tests 3
Average HIGH Pulse Width - tCH(avg) - Test Method of Implementation
The purpose of this test is to measure the average duty cycle of all the positive pulse widths within a
window of 200 consecutive cycles.
Signals of Interest
Mode Supported: DDR2, LPDDR2
Signal cycle of interest: READ or WRITE
Signal(s) of Interest:
• Clock Signal
Signals required to perform the test on the oscilloscope:
• Pin Under Test, PUT - any signal of interest, as defined above
Test Definition Notes from the Specification
Test References
See Table 42 - Timing Parameters by Speed Grade (DDR2-667 and DDR2-800) in the JEDEC
Standard JESD79-2E , Table 41 - Timing Parameters by Speed Grade (DDR2-1066) in the JESD208 ,
and Table 103 in the JESD209-2B.
Pass Condition
The tCH measurement value should be within the conformance limits as specified in the JEDEC
specification.
Table 12 Timing Parameters by Speed Grade (DDR2-667 and DDR2-800)
Parameter Symbol DDR2-667 DDR2-800 Units Specific
Notes
Min Max Min Max
Average clock HIGH pulse width tCH(avg) 0.48 0.52 0.48 0.52 tCK(avg) 35,36
Table 13 Timing Parameters by Speed Grade (DDR2-1066)
Parameter Symbol DDR2-1066 Units Specific
Notes
Min Max
Average clock HIGH pulse width tCH(avg) 0.48 0.52 tCK(avg) 30,31
Table 14 LPDDR2 AC Timing Table
Parameter Symbol Min
Max Min
t
CK
LPDDR2 Unit
1066 933 800 677 533 466*
5
400 333 266*
5
200*
5
Max.
Frequency
*4
533 466 400 333 266 233 200 166 133 100 MHz
Clock Timing
Average high
pulse width
t
CH
(avg)
Min 0.45
t
CK
(avg)
Max 0.55