Keysight Technologies D9020DDRC, Руководство пользователя

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15 Data Strobe Timing (DST) Tests
220 DDR2(+LP) Compliance Testing Methods of Implementation
tQH, DQ/DQS Output Hold Time From DQS - Test Method of Implementation
The purpose of this test is to verify that the time interval from the data output hold time (DQ rising
and falling edge) from the DQS (rising and falling edge) is within the conformance limit as specified in
the JEDEC specification.
Signals of Interest
Mode Supported: DDR2 and LPDDR2
Signal cycle of interest: READ
Signal(s) of Interest:
• Data Signal (supported by Data Strobe Signal)
Optional signal(s):
• Chip Select Signal (this signal is used to separate DQ signals from different rank of memory)
Signals required to perform the test on the oscilloscope:
• Data Signal, DQ
• Data Strobe Signal, DQS
• Chip Select Signal, CS (optional)
Test Definition Notes from the Specification
Table 135 Timing Parameters by Speed Grade (DDR2-400 and DDR2-533) & (DDR2-667 and DDR2-800)
Parameter Symbol DDR2-400 DDR2-533 Units Specific
Notes
Min Max Min Max
DQ/DQS output hold time from DQS tQH tHP-tQHS x tHP-tQHS x ps
Parameter Symbol DDR2-667 DDR2-800 Units Specific
Notes
Min Max Min Max
DQ/DQS output hold time from DQS tQH tHP-tQHS x tHP-tQHS x ps 39
Table 136 Timing Parameters by Speed Grade (DDR2-1066)
Parameter Symbol DDR2-1066 Units Specific
Notes
Min Max
DQ/DQS output hold time from DQS tQH tHP-tQHS x ps 34
Table 137 LPDDR2 AC Timing Table
Parameter Symbol Min
Max Min
t
CK
LPDDR2 Unit
1066 933 800 677 533 466*
5
400 333 266*
5
200*
5
Read Parameters*
14
DQ/DQS output
hold time from
DQS
tQH Max
t
QHP
- t
QHS
ps