Keysight Technologies D9020DDRC, Руководство пользователя

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17 Command and Address Timing (CAT) Tests
302 DDR2(+LP) Compliance Testing Methods of Implementation
tIH(base) - Address and Control Input Hold Time - Test Method of Implementation
The purpose of this test is to verify that the time interval from the address or control or
command/address (rising or falling edge) hold time to the associated clock crossing edge is within
the conformance limits as specified in the JEDEC specification.
Signals of Interest
Mode Supported: DDR2. LPDDR2
Signal cycle of interest: WRITE
Signal(s) of Interest:
• Address Signal OR Control Signal OR Command/Address
• Clock Signal
Signals required to perform the test on the oscilloscope:
• Address Signal OR Control Signal OR Command/Address
• Clock Signal
Test Definition Notes from the Specification
Table 208 Timing Parameters by Speed Grade (DDR2-400 and DDR2-533) & (DDR2-667 and DDR2-800)
Parameter Symbol DDR2-400 DDR2-533 Units Specific Notes
Min Max Min Max
Address and control input hold time tIH(base) 475 x 375 x ps 5,7,9,23
Parameter Symbol DDR2-667 DDR2-800 Units Specific Notes
Min Max Min Max
Address and control input hold time tIH(base) 275 x 250 x ps 5,7,9,23,29
Table 209 Timing Parameters by Speed Grade (DDR2-1066)
Parameter Symbol DDR2-1066 Units Specific Notes
Min Max
Address and control input hold time tIH(base) 200 x ps 5,7,9,20,24
Table 210 CA and CS_n Setup and Hold Base-Values for 1V/ns
Symbol LPDDR2 Unit Reference
1066 933 800 677 533 466
tIH(base) 90 120 160 240 330 390 ps V
IH/L(AC)
= V
REF(DC)
+/- 130mV
Symbol LPDDR2 Units Specific Notes
400 333 266 200
tIH(base) 400 540 700 950 ps V
IH/L(AC)
= V
REF(DC)
+/- 200mV