(No.22023)1-37
24,25~27
A10,A0 - A2
Row/column addresses are multiplexed on the same pins.
Row address : RA0 ~ RA10, Column address : CA0 ~ CA7
28
DQM2
Makes data output Hi-Z, tSHZ after the clock and masks the output.
Blocks data input when DQM active.
29
VDD
Power for the input buffers and core logic.
30
N.C
This pin is recommended to be left no connection on the device.
31
DQ16
Data input/output are multiplexed on the same pin.
32
VSSQ
Isolated ground for the output buffers to provide improved noise immunity.
33,34
DQ17,DQ18
Data inputs/outputs are multiplexed on the same pins.
35
VDDQ
Isolated power supply for the output buffers to provide improved noise immunity.
36,37
DQ19,DQ20
Data inputs/outputs are multiplexed on the same pins.
38
VSSQ
Isolated ground for the output buffers to provide improved noise immunity.
39,40
DQ21,DQ22
Data inputs/outputs are multiplexed on the same pins.
41
VDDQ
Isolated power supply for the output buffers to provide improved noise immunity.
42
DQ23
Data input/output are multiplexed on the same pin.
43
VDD
Power for the input buffers and core logic.
44
VSS
Ground for the input buffers and core logic.
45
DQ24
Data input/output are multiplexed on the same pin.
46
VSSQ
Isolated ground for the output buffers to provide improved noise immunity.
47,48
DQ25,DQ26
Data inputs/outputs are multiplexed on the same pins.
49
VDDQ
Isolated power supply for the output buffers to provide improved noise immunity.
50,51
DQ27,DQ28
Data inputs/outputs are multiplexed on the same pins.
52
VSSQ
Isolated ground for the output buffers to provide improved noise immunity.
53,54
DQ29,DQ30
Data inputs/outputs are multiplexed on the same pins.
55
VDDQ
Isolated power supply for the output buffers to provide improved noise immunity.
56
DQ31
Data input/output are multiplexed on the same pin.
57
N.C
This pin is recommended to be left no connection on the device.
58
VSS
Ground for the input buffers and core logic.
59
DQM3
Makes data output Hi-Z, tSHZ after the clock and masks the output.
Blocks data input when DQM active.
60~66
A3 - A9
Row/column addresses are multiplexed on the same pins.
Row address : RA0 - RA10, Column address : CA0 - CA7
67
CKE
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disables input buffers for power down mode.
68
CLK
Active on the positive going edge to sample all inputs.
69,70
N.C
This pin is recommended to be left no connection on the device.
71
DQM1
Makes data output Hi-Z, tSHZ after the clock and masks the output.
Blocks data input when DQM active.
72
VSS
Ground for the input buffers and core logic.
73
N.C
This pin is recommended to be left no connection on the device.
74
DQ8
Data input/output are multiplexed on the same pin.
75
VDDQ
Isolated power supply for the output buffers to provide improved noise immunity.
76,77
DQ9,DQ10
Data inputs/outputs are multiplexed on the same pins.
78
VSSQ
Isolated ground for the output buffers to provide improved noise immunity.
79,80
DQ11,DQ12
Data inputs/outputs are multiplexed on the same pins.
81
VDDQ
Isolated power supply for the output buffers to provide improved noise immunity.
82,83
DQ13,DQ14
Data inputs/outputs are multiplexed on the same pins.
84
VSSQ
Isolated ground for the output buffers to provide improved noise immunity.
85
DQ15
Data input/output are multiplexed on the same pin.
86
VSS
Ground for the input buffers and core logic.
Pin No.
Symbol
Function