(No.22023)1-23
SECTION 6
DESCRIPTION OF MAJOR ICS
6.1
74LCX32MTC-X (IC522) : OR gate
• Pin layout & Block diagram
• Truth table
6.2
74LCX373MTC-X (IC512,IC513) : Latch
• Pin layout
• Pin function
• Truth table
H = HIGH Voltage level
L = LOW Voltage level
Z = High impedance
X = Immaterial
O0 = Previous O0 before HIGH to LOW transition of latch enable
• Block diagram
6.3
TC74HC4072AF-X (IC611) : OR gate
• Block diagram
• Truth table
X : Don't care
1
1A
2
1B
3
1Y
4
2A
5
2B
6
2Y
7
14
13
12
11
10
9
8
GND
V
CC
4B
4A
4Y
3B
3A
3Y
(TOP VIEW)
INPUTS
OUTPUT
A
B
Y
L
L
L
L
H
H
H
L
H
H
H
H
Symbol
Description
D0~D7
Data inputs
LE
Latch enable input
OE
Output enable input
O0~O7
3-State latch outputs
1
OE
2
O0
3
D0
4
D1
5
O1
6
O2
7
20
19
18
17
16
15
14
D2
VCC
O7
D7
D6
O6
O5
D5
(TOP VIEW)
8
D3
9
O3
10
GND
13
12
11
D4
O4
LE
INPUTS
OUTPUT
LE
OE
Dn
On
X
H
X
Z
H
L
L
L
H
L
H
H
L
L
X
O0
O
L
D
D0
3
2
O0
11
1
LE
OE
O
L
D
D1
4
5
O1
O
L
D
D2
7
6
O2
O
L
D
D3
8
9
O3
O
L
D
D4
13
12
O4
O
L
D
D5
14
15
O5
O
L
D
D6
17
16
O6
O
L
D
D7
18
19
O7
1Y
1A
1B
1C
1D
NC
GND
1
2
3
4
5
6
7
14
13
12
11
10
9
8
Vcc
2Y
2D
2C
2B
2A
NC
A
B
C
D
Y
H
X
X
X
H
X
H
X
X
H
X
X
H
X
H
X
X
X
H
H
L
L
L
L
L