1-36 (No.22023)
6.14 K4S643232E-TC60 (IC505) : 512K x 32 bit x 4 banks synchronous DRAM
• Pin layout
• Block diagram
• Pin function
1
43
86
44
Pin No.
Symbol
Function
1
VDD
Power for the input buffers and core logic.
2
DQ0
Data input/output are multiplexed on the same pin.
3
VDDQ
Isolated power supply for the output buffers to provide improved noise immunity.
4,5
DQ1,DQ2
Data inputs/outputs are multiplexed on the same pins.
6
VSSQ
Isolated ground for the output buffers to provide improved noise immunity.
7,8
DQ3,DQ4
Data inputs/outputs are multiplexed on the same pins.
9
VDDQ
Isolated power supply for the output buffers to provide improved noise immunity.
10,11
DQ5,DQ6
Data inputs/outputs are multiplexed on the same pins.
12
VSSQ
Isolated ground for the output buffers to provide improved noise immunity.
13
DQ7
Data input/output are multiplexed on the same pin.
14
N.C
This pin is recommended to be left no connection on the device.
15
VDD
Power for the input buffers and core logic.
16
DQM0
Makes data output Hi-Z, tSHZ after the clock and masks the output.
Blocks data input when DQM active.
17
WE
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
18
CAS
Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
19
RAS
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
20
CS
Disables or enables device operation by masking or enabling all inputs except CLK, CKE and DQM.
21
N.C
This pin is recommended to be left no connection on the device.
22,23
BA0,BA1
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
CLK
ADD
LCKE
Address Register
LRAS LCBR LWE
CLK
CKE
CS
RAS
CAS
Timing Register
LCAS
Col. Buffer
LCBR
LRAS
WE
DQM
Column Decoder
Latency & Burst Length
Programming Register
LWCBR
LDQM
Output Buffer
Sense AMP
DQi
LWE
LDQM
I/O Control
512K x 32
512K x 32
512K x 32
512K x 32
Data Input Register
Bank Select
Row Decoder
Row Buffer
Refresh Counter