(No.22023)1-39
6.16 LM1117MP1.8-X (IC511) : Regulator
• Pin layout
• Block diagram
6.17 LP61L1024S-12-X (IC641) : SRAM
• Pin layout
• Block diagram
• Pin function
Top view
A
DJ/GND
OUTPUT
INPUT
GND (FIXED OUTPUT)
ADJ.(ADJUSTABLE OUTPUT)
V
OUT
V
IN
Thermal
Limit
Current
Limit
Substrate
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O1
I/O2
I/O3
VSS
VDD
A15
NC(CE2)
WE
A13
A8
A9
A11
OE
A10
CS1
I/O8
I/O7
I/O6
I/O5
I/O4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
SYMBOL
DESCRIPTION
A0 - A16
Address Input
I/O1 - I/O8
Data Input/Output
CS1, CS2
Chip Select Inputs
WE
Write Enable Input
OE
Output Enable Input
VDD
Power Supply
Vss
Ground
NC
No Connection
DECODER
CORE
ARRAY
CONTROL
DATA I/O
V
DD
Vss
CS2
CS1
OE
WE
A0
A16
I/O1
I/O8