Intergraph TDZ 2000, Настройка системы

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OS/2 Compatible Mode
When set to Yes, this setting optimizes the system for use with OS/2. The default is No.
Processor Microcode Update (Supervisor)
This parameter allows to you disable an installed processor patch, if the patch causes the
system to operate improperly. Any patch installed by Intergraph Computer Systems has been
certified for use with the system, so this parameter is set to Enabled by default. Use Disabled
if a non-Intergraph Computer Systems certified patch is applied and problems occur. This
parameter can be modified only by the Supervisor.
L1 and L2 Cache Mode
Allows you to choose between two processor cache modes: WriteBack (default) and
WriteThru.
L2 Cache ECC Mode
This parameter, when enabled, allows error checking and correction in the Level 2 cache in
the processor subsystem. Enabling ECC Mode can slow system performance. The default
for this parameter is Disabled.
System BIOS Cacheable
Setting this parameter to Enabled (default) makes the BIOS code cacheable, which improves
overall system performance.
C
x000, 16K Shadow
When the system boots, the BIOS code on ISA adapters is used directly from ROM
(Disabled), or it is copied from the board’s ROM to system RAM. Overall system
performance improves when copied to RAM (Enabled). When set to Cached (default), the
BIOS is copied to RAM and cached, further improving performance. An ISA board BIOS
executes faster from system board RAM than from the ISA board ROM. All of the ISA
Adapter ROM parameters are set to Cached by default.
D
x000, 16K Shadow
When the system boots, the BIOS code on ISA adapters is used directly from ROM
(Disabled, the default setting), or it is copied from the board’s ROM to system RAM.
Overall system performance improves when copied to RAM (Enabled). When set to Cached,
the BIOS is copied to RAM and cached, further improving performance. An ISA board
BIOS executes faster from system board RAM than from the ISA board ROM. All of the
ISA Adapter ROM parameters are set to Disabled by default.