16
64-bit Intel
®
Xeon
®
Processor with 800 MHz System Bus
(1 MB and 2 MB L2 Cache Versions) Specification Update
Summary Table of Changes
S63
X
Fixed
Writes to IA32_MISC_ENABLE may not update flags for both
logical processors
S64
X
Fixed
Execute Disable Bit set with CR4.PAE may cause livelock
S65
X
Fixed
SYSENTER or SYSEXIT instructions may experience
incorrect canonical address checking on processors
supporting Intel® Extended Memory 64 Technology (Intel®
EM64T)
S66
X
X
X
X
X
No Fix
Checking of Page Table Base Address may not match
Address Bit Width supported by the platform
S67
X
X
X
X
X
No Fix
IA32_MCi_STATUS MSR may improperly indicate that
additional MCA information may have been captured
S68
X
X
X
X
X
No Fix
With Trap Flag (TF) asserted, FP instruction that triggers
unmasked FP Exception may take single step trap before
retirement of instruction
S69
X
X
X
X
X
No Fix
PDE/PTE loads and continuous locked updates to the same
cache line may cause system livelock
S70
X
Fixed
MCA-corrected memory hierarchy error counter may not
increment correctly
S71
X
X
X
X
X
No Fix
Branch Trace Store (BTS) and Precise Event-Based
Sampling (PEBS) may update memory outside the
BTS/PEBS buffer
S72
X
X
X
Fixed
L-bit of CS and LMA bit of IA32_EFER register may have
erroneous value for one instruction following mode transition
in Hyper-Threading Technology-Enabled processor
supporting Intel® Extended Memory 64 Technology (Intel®
EM64T)
S73
X
X
X
X
Fixed
The base of an LDT (Local Descriptor Table) register may be
non-zero on a processor supporting Intel® Extended Memory
64 Technology (Intel® EM64T)
S74
X
Fixed
Unaligned Page-Directory-Pointer (PDPTR) Base with 32-bit
mode PAE (Page Address Extension) paging may cause
processor to hang
S75
X
X
X
X
X
No Fix
Memory ordering failure may occur with snoop filtering
third-party agents after issuing and completing a BWIL (Bus
Write Invalidate Line) or BLW (Bus Locked Write) transaction
S76
X
X
X
X
X
No Fix
Control Register 2 (CR2) can be updated during a REP
MOVS/STOS instruction with fast strings enabled
S77
X
X
X
X
X
No Fix
REP STOS/MOVS instructions with RCX >= 2^32 may cause
system hang
S78
X
X
X
X
Fixed
REP MOVS or REP STOS instruction with RCX >= 2^32 may
fail to execute to completion or may write to incorrect memory
locations on processors supporting Intel® Extended Memory
64 Technology (Intel® EM64T)
S79
X
X
X
X
X
Plan Fix
An REP LODSB or an REP LODSD or an REP LODSQ
instruction with RCX >= 2^32 may cause a system hang on
processors supporting Intel® Extended Memory 64
Technology (Intel® EM64T)
S80
X
X
X
X
Fixed
Data access which spans both canonical and non-canonical
address space may hang system
Errata (Sheet 4 of 5)
No.
D-0/
0F34h
E-0/
0F41h
G-1/
0F49h
N-0/
0F43h
R-0/
0F4Ah
Plans
Errata
