36
64-bit Intel
®
Xeon
®
Processor with 800 MHz System Bus
(1 MB and 2 MB L2 Cache Versions) Specification Update
Errata
Status:
For the steppings affected, see the
Summary Table of Changes
.
S67
IA32_MCi_STATUS MSR may improperly indicate that additional MCA
information may have been captured
Problem:
When a data parity error is detected and the bus queue is busy, the ADDRV and MISCV bits of the
IA32_MCi_STATUS register may be asserted even though the contents of the IA32_MCi_ADDR
and IA32_MCi_MISC MSRs were not properly captured.
Implication:
If this erratum occurs, the MCA information captured in the IA32_MCi_ADDR and
IA32_MCi_MISC registers may not correspond to the reported machine-check error, even though
the ADDRV and MISCV are asserted.
Workaround:
None at this time.
Status:
For the steppings affected, see the
Summary Table of Changes
.
S68
With Trap Flag (TF) asserted, FP instruction that triggers unmasked FP
Exception may take single step trap before retirement of instruction
Problem:
If an FP instruction generates an unmasked exception with the EFLAGS.TF = 1, it is possible for
external events to occur, including a transition to a lower power state. When resuming from a lower
power state, it may be possible to take the single step trap before the execution of the original FP
instruction completes.
Implication:
When this erratum occurs, a single step trap will be taken unexpectedly.
Workaround:
None at this time.
Status:
For the steppings affected, see the
Summary Table of Changes
.
S69
PDE/PTE loads and continuous locked updates to the same cache line may
cause system livelock
Problem:
In a multi-processor configuration, if one processor is continuously doing locked updates to a
cache line that is being accessed by another processor doing a page table walk, the page table walk
may not complete.
Implication:
Due to this erratum, the system may livelock until some external event interrupts the locked
update. Intel has not observed this erratum with any commercially available software.
Workaround:
None at this time.
Status:
For the steppings affected, see the
Summary Table of Changes
.
S70
MCA-corrected memory hierarchy error counter may not increment
correctly
Problem:
An MCA-corrected memory hierarchy error counter can report a maximum of 255 errors. Due to
the incorrect increment of the counter, the number of errors reported may be incorrect.
Implication:
Due to this erratum, the MCA counter may report an incorrect number of soft errors.
Workaround:
None at this time.
Status:
For the steppings affected, see the
Summary Table of Changes
.
S71
Branch Trace Store (BTS) and Precise Event-Based Sampling (PEBS) may
update memory outside the BTS/PEBS buffer
Problem:
If the BTS/PEBS buffer is defined such that:
1. The difference between the BTS/PEBS buffer base and the BTS/PEBS absolute maximum is
not an integer multiple of the corresponding record sizes,
