Intel SL7PG - Xeon 3.4 GHz/800MHz/1MB Cache CPU Processor, Спецификация

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64-bit Intel
®
Xeon
®
Processor with 800 MHz System Bus 15
(1 MB and 2 MB L2 Cache Versions) Specification Update
Summary Table of Changes
S43 X X Fixed Recursive page walks may cause a system hang
S44 X Fixed WRMSR to bit[0] of IA32_MISC_ENABLE register changes
only one logical processor on a Hyper-Threading Technology
enabled processor
S45 X X X X Fixed VERR/VERW instructions may cause #GP fault when
descriptor is in non-canonical space
S46 X Fixed INS or REP INS flows save an incorrect memory address for
SMI on processors supporting Intel® Extended Memory 64
Technology (Intel® EM64T)
S47 X Fixed FXSAVE instruction may result in incorrect data on
processors supporting Intel® Extended Memory 64
Technology (Intel® EM64T)
S48 X X Fixed The base of a null segment may be non-zero on a processor
supporting Intel® Extended Memory 64 Technology (Intel®
EM64T)
S49 X X Fixed Upper 32 bits of FS/GS with null base may not get cleared in
Virtual-8086 Mode on processors with Intel® Extended
Memory 64 Technology (Intel® EM64T) Enabled
S50 X X X X X No Fix Processor may fault when the upper 8 bytes of segment
selector is loaded from a far jump through a call gate via the
Local Descriptor Table
S51 X Fixed Compatibility mode STOS instructions may alter RSI register
results on a processor supporting Intel® Extended Memory 64
Technology (Intel® EM64T)
S52 X Fixed LDT descriptor which crosses 16 bit boundary access does
not cause a #GP fault on a processor supporting Intel®
Extended Memory 64 Technology (Intel® EM64T)
S53 X Fixed Upper reserved bits are incorrectly checked while loading
PDPTR's on a processor supporting Intel® Extended Memory
64 Technology (Intel® EM64T)
S54 X X X X X No Fix Loading a stack segment with a selector that references a
non-canonical address can lead to a #SS fault on a processor
supporting Intel® Extended Memory 64 Technology (Intel®
EM64T)
S55 X Fixed CPUID instruction incorrectly reports CMPXCH16B as
supported
S56 X X X X X No Fix FXRSTOR may not restore non-canonical effective addresses
on processors with Intel® Extended Memory 64 Technology
(Intel® EM64T) enabled
S57 X X X X X No Fix A push of ESP that faults may zero the upper 32-bits of RSP
S58 X Fixed Enhanced halt state (C1E) voltage transition may affect a
system’s power management in a Hyper-Threading
Technology enabled processor
S59 X X X X No Fix Enhanced halt state (C1E) may not be entered in a
Hyper-Threading Technology enabled processor
S60 X Fixed When the Execute Disable Bit function is enabled a page fault
in a mispredicted branch may result in a page fault exception
S61 X Fixed Execute Disable Bit set with AD assist may cause livelock
S62 X X Fixed The Execute Disable Bit fault may be reported before other
types of page fault when both occur
Errata (Sheet 3 of 5)
No.
D-0/
0F34h
E-0/
0F41h
G-1/
0F49h
N-0/
0F43h
R-0/
0F4Ah
Plans Errata