6
64-bit Intel
®
Xeon
®
Processor with 800 MHz System Bus
(1 MB and 2 MB L2 Cache Versions) Specification Update
Preface
Preface
This document is an update to the specifications contained in the following documents:
1.
64-bit Intel
®
Xeon
®
Processor with 2 MB L2 Cache Datasheet
(Document Number 306249)
Link: http://developer/design/xeon/datashts/306249.htm
2.
Intel
®
Xeon
®
Processor with 800 MHz System Bus Datasheet
(Document Number 302355)
Link: http://developer/design/xeon/datashts/302355.htm
This document is intended for hardware system manufacturers and software developers of
applications, operating systems, or tools.
Nomenclature
S-Spec Number
is a five-digit code used to identify products. Products are differentiated by their
unique characteristics, e.g., core speed, L2 cache size, package type, etc. as described in the
processor identification information table. Care should be taken to read all notes associated with
each S-Spec number.
Errata
are design defects or errors. Errata may cause the processor’s behavior to deviate from
published specifications. Hardware and software designed to be used with any given processor
must assume that all errata documented for that processor are present on all devices unless
otherwise noted.
Specification Changes
are modifications to the current published specifications. These changes
will be incorporated in the next release of the specifications.
Specification Clarifications
describe a specification in greater detail or further highlight a
specification’s impact to a complex design situation. These clarifications will be incorporated in
the next release of the specifications.
Documentation Changes
include typos, errors, or omissions from the current published
specifications. These changes will be incorporated in the next release of the specifications.
