24
64-bit Intel
®
Xeon
®
Processor with 800 MHz System Bus
(1 MB and 2 MB L2 Cache Versions) Specification Update
Errata
S12
Processor issues inconsistent transaction size attributes for locked
operation
Problem:
When the processor is in the Page Address Extension (PAE) mode and detects the need to set the
Access and/or Dirty bits in the page directory or page table entries, the processor sends an 8-byte
load lock onto the system bus. A subsequent 8 byte store unlock is expected, but instead a 4 byte
store unlock occurs. Correct data is provided since only the lower bytes change, however external
logic monitoring the data transfer may be expecting an 8-byte store unlock.
Implication:
This erratum affects no known commercially available chipsets.
Workaround:
None at this time.
Status:
For the steppings affected, see the
Summary Table of Changes
.
S13
When the processor is in the system management mode (SMM), Debug
registers may be fully writeable
Problem:
When in system management mode (SMM), the processor executes code and stores data in the
SMRAM space. When the processor is in this mode and writes are made to DR6 and DR7, the
processor should block writes to the reserved bit locations. Due to this erratum, the processor may
not block these writes. This may result in invalid data in the reserved bit locations.
Implication:
Reserved bit locations within DR6 and DR7 may become invalid.
Workaround:
Software may perform a read/modify/write when writing to DR6 and DR7 to ensure that the values
in the reserved bits are maintained.
Status:
For the steppings affected, see the
Summary Table of Changes
.
S14
Shutdown and IERR# may result due to a machine check exception on a
Hyper-Threading Technology enabled processor
Problem:
When a MCE occurs due to an internal error, both logical processors on a Hyper-Threading (HT)
Technology enabled processor normally vector to the MCE handler. However, if one of the logical
processors is in the “Wait for SIPI” state, that logical processor will not have a MCE handler and
will shut down and assert IERR#.
Implication:
A processor with a logical processor in the “Wait for SIPI” state will shut down when an MCE
occurs on the other thread.
Workaround:
None at this time.
Status:
For the steppings affected, see the
Summary Table of Changes
.
S15
Processor may hang under certain frequencies and 12.5% STPCLK# duty
cycle
Problem:
If a system deasserts STPCLK# at a 12.5% duty cycle, and the processor is running below 2 GHz,
and the processor thermal control circuit (TCC) on-demand clock modulation is active, the
processor may hang. This erratum does not occur under the automatic mode of the TCC.
Implication:
When this erratum occurs, the processor will hang.
Workaround:
If use of the on-demand mode of the processor's TCC is desired in conjunction with STPCLK#
modulation, then assure that STPCLK# is not asserted at a 12.5% duty cycle.
Status:
For the steppings affected, see the
Summary Table of Changes
.
