40
64-bit Intel
®
Xeon
®
Processor with 800 MHz System Bus
(1 MB and 2 MB L2 Cache Versions) Specification Update
Errata
S82
A 64-bit value of Linear Instruction Pointer (LIP) may be reported incorrectly
in the Branch Trace Store (BTS) memory record or in the Precise Event
Based Sampling (PEBS) memory record
Problem:
On a processor supporting Intel EM64T,
•
If an instruction fetch wraps around the 4G boundary in Compatibility mode, the 64-bit value
of LIP in the BTS memory record will be incorrect (upper 32 bits will be set to FFFFFFFFh
when they should be 0).
•
If a PEBS event occurs on an instruction whose last byte is at memory location FFFFFFFFh,
the 64-bit value of LIP in the PEBS record will be incorrect (upper 32 bits will be set to
FFFFFFFFh when they should be 0).
Implication:
Intel has not observed this erratum on any commercially available software.
Workaround:
None identified.
Status:
For the steppings affected, see the
Summary Table of Changes
.
S83
It is possible that two specific invalid opcodes may cause unexpected
memory accesses
Problem:
A processor is expected to respond with an undefined opcode (#UD) fault when executing either
opcode 0F 78 or a Grp 6 Opcode with bits 5:3 of the Mod/RM field set to 6, however the processor
may respond instead, with a load to an incorrect address.
Implication:
This erratum may cause unpredictable system behavior or system hang.
Workaround:
It is possible for BIOS to contain a workaround for this erratum.
Status:
For the steppings affected, see the
Summary Table of Changes
.
S84
At core-to-bus ratios of 16:1 and above Defer Reply transactions with
non-zero REQb values may cause a Front Side Bus stall
Problem:
Certain processors are likely to hang the Front Side Bus (FSB) if the following conditions are met:
1. A Defer Reply transaction has a REQb[2:0] value of either 010b, 011b, 100b, 110b, or 111b,
and
2. The operating bus ratio is 16:1 or higher.
When these conditions are met, the processor may incorrectly and indefinitely assert a snoop stall
for the Defer Reply transaction. Such an event will block further progress on the FSB.
Implication:
If this erratum occurs, the system may hang. Intel has not observed this erratum with any
commercially available system.
Workaround:
None identified.
Status:
For the steppings affected, see the
Summary Table of Changes
.
S85
Processor may issue Frost Side Bus transactions up to 6 clocks after
RESET# is asserted
Problem:
The processor may issue transactions beyond the documented 3 Front Side Bus (FSB) clocks and
up to 6 FSB clocks after RESET# is asserted in the case of a warm reset. A warm reset is where the
chipset asserts RESET# when the system is running.
Implication:
The processor may issue transactions up to 6 FSB clocks after RESET# is asserted.
Workaround:
None identified.
Status:
For the steppings affected, see the
Summary Table of Changes
.
