64-bit Intel
®
Xeon
®
Processor with 800 MHz System Bus
27
(1 MB and 2 MB L2 Cache Versions) Specification Update
Errata
error status register is being written due to a previous error, bit 6 does not get set and illegal vector
errors are not flagged.
Implication:
The xAPIC may not report some Illegal Vector errors when they occur at approximately the same
time as other xAPIC errors. The other xAPIC errors will continue to be reported.
Workaround:
None at this time.
Status:
For the steppings affected, see the
Summary Table of Changes
.
S25
Enabling no-eviction mode (NEM) may prevent the operation of the second
logical processor in a Hyper-Threading Technology enabled boot strap
processor (BSP)
Problem:
In an HT Technology enabled system, when NEM is enabled by setting Bit 0 of MSR 080h
(IA32_BIOS_CACHE_AS_RAM), the second logical processor associated with the BSP may fail
to wake up from “Wait-for-SIPI” state.
Implication:
In an HT Technology enabled system, the second logical processor associated with the BSP may
not respond to SIPI. The OS will continue to operate but with one less logical processor than
expected.
Workaround:
It is possible for the BIOS to contain a workaround for this erratum.
Status:
For the steppings affected, see the
Summary Table of Changes
.
S26
TPR (Task Priority Register) updates during voltage transitions of power
management events may cause a system hang
Problem:
Systems with Echo TPR Disable (R/W) bit (bit [23] of the IA32_MISC_ENABLE register) set to
'0' (default), where xTPR messages are being transmitted on the system bus to the processor, may
experience a system hang during voltage transitions caused by power management events.
Implication:
This may cause a system hang during voltage transitions of power management events.
Workaround:
It is possible for the BIOS to contain a workaround for this erratum. The BIOS workaround
disables the Echo TPR updates on the affected steppings.
Status:
For the steppings affected, see the
Summary Table of Changes
.
S27
Interactions between the instruction translation lookaside buffer (ITLB) and
the instruction streaming buffer may cause unpredictable software behavior
Problem:
Complex interactions within the instruction fetch/decode unit may make it possible for the
processor to execute instructions from an internal streaming buffer containing stale or incorrect
information.
Implication:
When this erratum occurs, an incorrect instruction stream may be executed resulting in
unpredictable software behavior.
Workaround:
It is possible for the BIOS to contain a workaround for this erratum.
Status:
For the steppings affected, see the
Summary Table of Changes
.
S28
STPCLK# signal assertion under certain conditions may cause a system
hang
Problem:
The assertion of STPCLK# signal before a logical processor awakens from the “Wait-for-SIPI”
state for the first time, may cause a system hang. A processor supporting HT Technology may fail
to initialize appropriately, and may not issue a Stop Grant Acknowledge special bus cycle in
response to the second STPCLK# assertion.
Implication:
When this erratum occurs in an HT Technology enabled system, it may cause a system hang.
