64-bit Intel
®
Xeon
®
Processor with 800 MHz System Bus
31
(1 MB and 2 MB L2 Cache Versions) Specification Update
Errata
S43
Recursive page walks may cause a system hang
Problem:
A page walk, accessing the same page table entry multiple times but at different levels of the page
table, which causes the page table entry to have its Access bit set may result in a system hang.
Implication:
When this erratum occurs, the system may experience a hang.
Workaround:
It is possible for the BIOS to contain a workaround for this erratum.
Status:
For the steppings affected, see the
Summary Table of Changes
.
S44
WRMSR to bit[0] of IA32_MISC_ENABLE register changes only one logical
processor on a Hyper-Threading Technology enabled processor
Problem:
On an HT Technology enabled processor, a write to the fast-strings feature bit[0] of
IA32_MISC_ENABLE register changes the setting for the current logical processor only.
Implication:
Due to this erratum, the non-current logical processor may not update fast-strings feature bit[0] of
IA32_MISC_ENABLE register.
Workaround:
BIOS may set the fast-strings enable bit on both logical processors to workaround this erratum. It is
possible for the BIOS to contain a workaround for this erratum.
Status:
For the steppings affected, see the
Summary Table of Changes
.
S45
VERR/VERW instructions may cause #GP fault when descriptor is in
non-canonical space
Problem:
If a descriptor referenced by the selector specified for the
VERR
or
VERW
instructions is in
non-canonical space, it may incorrectly cause a #GP fault on a processor supporting Intel
®
Extended Memory 64 Technology (Intel
®
EM64T).
Implication:
Operating systems or drivers that reference a selector in non-canonical space may experience an
unexpected #GP fault. Intel has not observed this erratum with any commercially available
software.
Workaround:
None at this time.
Status:
For the steppings affected, see the
Summary Table of Changes
.
S46
INS or REP INS flows save an incorrect memory address for SMI on
processors supporting Intel
®
Extended Memory 64 Technology (Intel
®
EM64T)
Problem:
In IA-32e mode of the Intel EM64T processor, an
INS
or an
REP INS
instruction, followed by an
SMI, may save an incorrect memory address to the System Management Mode (SMM) save state
location.
Implication:
Due to this erratum, the SMM macro-handler may use the incorrect memory address while
reproducing the I/O access of SMI.
Workaround:
It is possible for the BIOS to contain a workaround for this erratum.
Status:
For the steppings affected, see the
Summary Table of Changes
.
S47
FXSAVE instruction may result in incorrect data on processors
supporting Intel
®
Extended Memory 64 Technology (Intel
®
EM64T)
Problem:
In IA-32e mode of the Intel EM64T processor, the upper 32 bits of the FDP value written out to
memory by the
FXSAVE
instruction may be incorrect.
Implication:
This erratum may cause incorrect data to be saved into the memory.
Workaround:
It is possible for the BIOS to contain a workaround for this erratum.
Status:
For the steppings affected, see the
Summary Table of Changes
.
