93
Memory Controller
Table 48.
DDR 333 Embedded Registered/Unbuffered Clock Routing Recommendations
Parameter
Routing Guideline
Reference Plane
•
Route over unbroken ground plane
Preferred Topology
•
Stripline routing is recommended for the clock
signals. Micro-strip will work with strict adherence
to all routing recommendations. Careful
simulation and timing analysis of ADD/CMD
signals is recommended.
Breakout Termination, Fan-in and Fanout width and
spacing
5 mils x 5 mils. Microstrip is recommended for pin
escapes and terminations.
Trace Impedance
Differential Target impedance of 100 Ohms +/-15%
(Applies to both Buffered and Unbuffered Topologies)
Trace Spacing (trace edge to edge)
5 mils. for breakout region
>20 mils. between any other signals or vias including
other clock pairs.
Registered Termination
None required
Un-buffered Termination
•
22 ohms +/-5% series termination on each
differential leg after breakout route
•
Post PLL and Unbuffered SDRAM Clock areas to
be Routed as T Point differential as per JEDEC
Unbuffered and Registered Post PLL Clock
Topology
Length matching Requirements:
•
The package lengths from Die to Ball provided in
must be accounted for when length
matching.
•
See respective registered
and
unbuffered
tables Topology/ Trace
Length tables for additional information.
•
Within Differential Clock pairs
•
+/- 0.025” max. within Pairs [Intra-pair]
•
Registered Clock from IOP Die to PLL Input with
Respect to DQS
•
With-in +/- 1.0” of all strobes (DQS0-8) (strobe
length measured from IOP die to SDRAM)
•
Registered Clock from IOP Die to PLL Input with
Respect to Add/CMD/Control
•
1.0” to 2.0” longer than Add/CMD/Control
(Add/CMD/Control length measured from IOP die
to Register input)
•
Un-buffered Clock from IOP Die to SDRAM input
with respect to DQS
•
With-in +/- 1.0” of associated strobe (DQS) (strobe
length measured from IOP die to SDRAM)
•
Un-buffered Clock from IOP Die to SDRAM input
with respect to Add/CMD/Control
•
1.0” to 2.0” longer than Add/CMD/Control from
(Add/CMD/Control length measured from IOP die
to SDRAM input)
•
Unbuffered Clock Pairs
•
+/- 0.1” max. between the 3 pairs of Unbuffered
Clocks (clock length measured from IOP die to
SDRAM)
Number of vias
•
For Registered: maximum of 3 pairs from IOP to
PLL
•
For Unbuffered: maximum of 4 pairs.
Routing Guideline
All un-buffered clocks utilized in memory
implementations must be load balanced. Use
capacitors equal to the SDRAM’s clock input
capacitance to balance loading across all the clocks
used. Topology shown is based on a Raw B
implementation. Refer to JEDEC Un-buffered DIMM
specs. for Raw Card C implementation specifics.
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