132
Power Delivery
9.2
Power Failure
This section describes the power failure sequence and associated circuitry that is needed to prevent
data loss during a power failure. While the host assumes all written data is stored on the
non-volatile disk subsystem, the IOP must ensure that eventually all the data in the disk cache is
actually stored onto disk. The power supply could fail to provide power to the I/O subsystem in the
case of a power outage or a failed power supply. It is imperative that the cached data within the
IOP’s local memory is not lost. If power fails, the local memory subsystem must remain powered
with a battery backup and some agent must continue to refresh at the appropriate interval specified
by the memory component datasheet.
9.2.1
Theory of Operation
DDR SDRAM technology provides a simple way of enabling data preservation through the
self-refresh
command. This command is issued by the memory controller and the DDR SDRAM
will refresh itself autonomously with internal logic and timers. The DDR SDRAM device will
remain in self-refresh mode as long as:
1. The device continues to be powered.
2.
CKE
is held low until the memory controller is ready to control the DDR SDRAM once again.
Power to the DDR SDRAM subsystem is ensured with an adequate battery backup and a reliable
method for switching between system power and battery power. The memory controller is
responsible for deasserting
CKE[1:0]
when issuing the
self-refresh
command but while power
gradually drops,
CKE[1:0]
must
remain deasserted regardless of the state of V
cc
powering the
80331.
9.2.2
Power Failure Sequence
Upon initial power-up, a power supply provides appropriate voltage to the system. The voltage
level increases at a rate dependent on the type of power supply used and components in the system.
In the specification, T
fail
is defined as the time when
P_RST#
is asserted in response to the power
rail going out of specification. T
fail
is the minimum of:
•
500 ns from either power rail going out of specification (exceeding specified tolerances by
more than 500 mV).
•
100 ns from the 5 V rail falling below the 3.3 V rail by more than 300 mV.
This proposal makes specific assumptions about the system behavior during a power failure. When
the below assumptions are not guaranteed, it is the responsibility of the vendor to ensure them.
•
P_RST#
is asserted to 80331 when there is at least 2
µ
s of reliable power remaining. This is
required so that the memory controller can execute the power failure state machine in response
to the assertion of
P_RST#.
For storage applications, it is imperative that data cached within DDR memory system not be lost in a
power failure condition. To prevent this from happening the local DDR memory needs to be saved with
provisions for battery backup, to allow DDR data to be saved using the refresh mode at an appropriate
interval until power is restored. The DDR has a self-refresh command that can be invoked as long as the
device remains powered and
CKE
is held low. Power to DDR SDRAM is ensured with an automatic
switch over to backup battery power when the system power is lost. Battery backup needs to maintain
power on DDR voltages
V
DD
,
V
DDQ
and
V
REF
to prevent data loss. Refer to the
Intel
®
80331 I/O
Processor Developer’s Manual
, for more information about this Power Failure Mode.
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