Intel 80331, Руководство по конструкции

Страница: 102 / 148

102
Intel® 80331 I/O Processor Design Guide
Memory Controller
7.5.1 Simulation Conditions
•
Motherboard 50 ohm single ended impedance s/- 15% tolerance
•
Add-in Card 60 ohm single ended impedance s/- 15% tolerance
•
Clock Target Differential Impedance 100 ohms and 50 ohms single-ended impedance
•
One Die Termination - ODT value of 75
Ω
was assumed for all DDR II simulations.
•
Memory Model Micron U26 and Intel generic models
•
PLL Clock - ICS ICSU877
•
Register - IDT IDT74SSTU32864
•
DIMM models and topologies used the JEDEC model as a reference.
•
For unbuffered embedded and post PLL/register the JEDEC standard recommendations were
used as a reference.
•
Vias are modeled for all topologies with equal number of vias for differential pair
•
Package - actual extracted package model.
•
Spacing recommendations are for trace edge to edge except for differential pairs in which
center to center was specified.
•
Timing analysis was conducted.
•
ISI Pattern was simulated for all the major topologies.
•
Signal Quality analysis covered for Rising flight time, Falling flight time, Low to high
ring-back (noise margin high), High to Low ring-back (noise margin Low), and Low and High
Overshoot.
•
Crosstalk Analysis was performed for all the major interfaces with actual package models.
•
Frequency: 200MHz (DDR 400 MT/s)
The topologies simulated are listed in Table 56 .
Table 56. DDR II Topologies Simulated
DIMM (Registered) Embedded
1. DQ/DQS
• Read- RAW A, RAWB
• Write -RAW A, RAW B
1. DQ/DQS
• Read- Single Bank
• Write - Single Bank
2. Clock
• Buffered - controller to PLL
• Unbuffered
2. Clock
• Controller to PLL
• Post-PLL
• PLL to SDRAM
• PLL to Register
• PLL to Feedback
3. Address/CMD
• Registered - RAWA, RAWB
configurations
3. Address/CMD
• write single bank non ECC and
ECC
• Post Register - single bank
ECC and non ECC