Infineon C513AO, Руководство пользователя

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User’s Manual 6-53 05.99
On-Chip Peripheral Components
C513AO
Note: SSCCON must be programmed only when the SSC is idle. Modifying the contents of
SSCCON while a transmission is in progress will corrupt the current transfer and will lead to
unpredictable results.
CPOL Clock Polarity
This bit controls the polarity of the shift clock and in conjunction with the CPHA bit
which clock edges are used for sample and shift.
CPOL = 0: SCLK idle state is low.
CPOL = 1: SCLK idle state is high.
CPHA Clock Phase
This bit controls in conjunction with the CPOL bit controls which clock edges are
used for sample and shift
CPHA = 0: The first clock edge of SCLK is used to sample the data, the second
to shift the next bit out at STO.
In Master Mode the transmitter will provide the first data bit on STO
immediately after the data was written into the STB register.
In Slave Mode the transmitter (if enabled via TEN) will shift out the
first data bit with the falling edge of SLS.
CPHA = 1: The first data bit is shifted out with the first clock edge of SCLK and
sampled with the second clock edge
BRS2,
BRS1,
BRS0 Baudrate Selection bits
These bits select one of the possible divide factors for generating the baudrate
from the microcontroller clock rate
f
osc
. The baudrate is defined by
Baudrate = f
osc
/Devidefactor = f
osc
/(4
×
2
BRS(2-0)
),
for BRS (2-0)
≠
0.
Bit Function
BRS(2-0) Divide
Factor Baudrate for
f
osc
= 7.68 MHz
Baudrate for
f
osc
= 12 MHz
0 reserved reserved reserved
1 8 960 kBaud 1.5 MBaud
2 16 480 kBaud 750 kBaud
3 32 240 kBaud 375 kBaud
4 64 120 kBaud 187,5 kBaud
5 128 60 kBaud 93,75 kBaud
6 256 30 kBaud 46,875 kBaud
7 512 15 kBaud 23,44 kBaud