User’s Manual
6-37
05.99
On-Chip Peripheral Components
C513AO
(thus at
f
OSC
/12). As a baudrate generator, however, it increments every state time (
f
OSC
/2). In that
case, the baudrate is given by the formula
Modes 1 and 3 baudrate =
f
OSC
/32
×
[65536 – (RC2H, RC2L)]
where (RC2H, RC2L) is the content of RC2H and RC2L taken as a 16-bit unsigned integer.
Note that the rollover in TH2 does not set TF2, and will not generate an interrupt. Therefore, the
Timer 2 interrupt need not be disabled when Timer 2 is in Baudrate Generator Mode. Note too, that
if EXEN2 is set, a 1-to-0 transition in T2EX can be used as an extra external interrupt, if desired.
Note also that when Timer 2 is running (TR2 = 1) in “timer” function in Baudrate Generator Mode,
TH2 or TL2 should not be read or written to. Under these conditions, the timer is incremented every
state time, and the results of a read or write may not be accurate. The RC registers may be read,
but should not be written to, because a write might overlap a reload and cause write and/or reload
errors. In such a case, turn the timer off (clear TR2) before accessing Timer 2 or RC registers.
6.3.4 Details about Mode 0
Serial data enters and exists through RXD. TXD outputs the shift clock. Eight data bits are
transmitted/received with LSB first. The baudrate is fixed at
f
OSC
/12. Figure 6-21 shows a simplified
functional diagram of the serial port in Mode 0. The associated timing is illustrated in Figure 6-22.
Transmission is initiated by any instruction that uses SBUF as a destination register. The “WRITE
to SBUF” signal at S6P2 also loads a “1” into the 9th position of the transmit shift register and tells
the TX control block to commence a transmission. The internal timing is such that one full machine
cycle will elapse between “WRITE to SBUF”, and activation of SEND.
SEND enables output of the shift register to the alternate output function line of P3.0, and enables
SHIFT CLOCK to the alternate output function line of P3.1. SHIFT CLOCK is low during S3, S4 and
S5 of every machine cycle, and high during S6, S1 and S2. At S6P2 of every machine cycle in which
SEND is active, the contents of the transmit shift register are shifted to the right one position.
As data bits shift out to the right, “0”s come in from the left. When the Most Significant Bit (MSB) of
the data byte is at the output position of the shift register, the “1” which was initially loaded into the
9th position is just to the left of the MSB, and all positions to the left of that contain “0”s. This
condition flags the TX control block to do one last shift and then deactivate SEND and set TI. Both
of these actions occur at S1P1 of the 10th machine cycle after “WRITE to SBUF”.
Reception is initiated by the condition REN = 1 and R1 = 0. At S6P2 of the next machine cycle, the
RX control unit writes the bits 1111 1110 to the Receive Shift Register, and in the next clock phase
activates RECEIVE.
RECEIVE enables SHIFT CLOCK to the alternate output function line of P3.1. SHIFT CLOCK
makes transitions at S3P1 and S6P1 of every machine cycle. At S6P2 of every machine cycle in
which RECEIVE is active, the contents of the receive shift register are shifted to the left one position.
The value that comes in from the right is the value that was sampled at the P3.0 pin at S5P2 of the
same machine cycle.
As a data bit comes in from the right, “1”s shift out to the left. When the “0” which was initially loaded
into the rightmost position arrives at the leftmost position in the shift register, it flags the RX control
block to do one last shift and load SBUF. At S1P1 of the 10th machine cycle after the write to SCON
that cleared RI, RECEIVE is cleared and RI is set.
