User’s Manual
2-4
05.99
Fundamental Structure
C513AO
2.2
CPU Timing
A machine cycle consists of six states (twelve oscillator periods). Each state is divided into two
phases. In Phase 1, the Phase 1 clock is active; in Phase 2, the Phase 2 clock is active. Thus, a
machine cycle consists of twelve oscillator periods, numbered S1P1 (State 1, Phase 1) through
S6P2 (State 6, Phase 2). Each state lasts for two oscillator periods. Typically, arithmetic and logical
operations take place during Phase 1 and internal register-to-register transfers take place during
Phase 2.
The diagrams in Figure 2-2 show the fetch/execute timing related to the internal states and phases.
Since these internal clock signals are not user-accessible, the XTAL2 oscillator signal and the
Address Latch Enable (ALE) signal are shown for external reference. ALE is normally activated
twice during each machine cycle: once during S1P2 and S2P1, and again during S4P2 and S5P1.
Execution of a one-cycle instruction begins at S1P2, when the op-code is latched into the instruction
register. If it is a two-byte instruction, the second reading takes place during S4 of the same
machine cycle. If it is a one-byte instruction, there is still a fetch at S4, but the byte read (which would
be the next op-code) is ignored (discarded fetch), and the program counter is not incremented. In
any case, execution is completed at the end of S6P2.
Figure 2-2 (a) and (b) show the timing for a 1-byte, 1-cycle instruction and for a 2-byte, 1-cycle
instruction, respectively.
Most C513AO instructions are executed in one cycle. Multiply (MUL) and divide (DIV) are the only
instructions that take more than two cycles to complete; they take four cycles. Normally, two code
bytes are fetched from the program memory during every machine cycle. The only exception to this
is execution of a MOVX instruction. MOVX is a one-byte, 2-cycle instruction that accesses external
data memory. During a MOVX, the two fetches in the second cycle are skipped while the external
data memory is being addressed and strobed. Figure 2-2 (c) and (d) show the timing for a normal
1-byte, 2-cycle instruction and for a MOVX instruction, respectively.
