External Bus Interface
C513AO
User’s Manual
4-1
05.99
4
External Bus Interface
The C513AO allows for external memory expansion. The functionality and implementation of the
external bus interface is identical to the common interface for the 8051 architecture with one
exception: if the C513AO is used in systems with no external memory, the generation of the ALE
signal can be suppressed. By resetting bit EALE in the SFR SYSCON register, the ALE signal will
not be generated externally. This feature reduces RFI emissions of the system.
4.1
Accessing External Memory
It is possible to differentiate between accesses to external program memory and external data
memory or other peripheral components. This differentiation is made by hardware. Accesses to
external program memory use the signal PSEN (Program Store Enable) as a read strobe. Accesses
to external data memory use RD and WR (alternate functions of P3.7 and P3.6) to strobe the
memory. Port 0 and Port 2 (with exceptions) are used to provide data and address signals. In this
section, only Port 0 and Port 2 functions relevant to external memory accesses are described.
Fetches from external program memory always use 16-bit addresses. Accesses to external data
memory can use either 16-bit addresses (MOVX @DPTR) or 8-bit addresses (MOVX @Ri).
4.1.1 Role of P0 and P2 as Data/Address Bus
When used for accessing external memory, Port 0 provides the data byte time-multiplexed with the
low byte of the address. In this state, Port 0 is disconnected from its own port latch, and the address/
data signal drives both FETs in the Port 0 output buffers. Thus, in this application, the Port 0 pins
are not open-drain outputs and do not require external pullup resistors.
During any access to external memory, the CPU writes FFH to the Port 0 latch (the Special Function
Register), thus obliterating whatever information the Port 0 SFR may have been holding.
Whenever a 16-bit address is used, the high byte of the address comes out on Port 2, where it is
held for the duration of the read or write cycle. During this time, the Port 2 lines are disconnected
from the Port 2 latch (the Special Function Register). Thus, the Port 2 latch does not need to contain
“1”s, and the contents of the Port 2 SFR are not modified. If the XRAM is enabled, at 16-bit address
accesses with address values within the XRAM address space, no external bus cycle will be seen,
but the internal XRAM will be accessed.
If an 8-bit address is used (MOVX @Ri), the contents of the Port 2 SFR remain at the Port 2 pins
throughout the external memory cycle. This will facilitate paging. It should be noted that, if a Port 2
pin outputs an address bit that is a “1”, strong pull-ups will be used for the entire read/write cycle
and not only for two oscillator periods. Regardless of the address, if the XRAM is enabled, no
external bus cycle will be seen.
