Interrupt System
C513AO
User’s Manual
7-9
05.99
SSC Interrupt
is generated by a logical OR of flag WCOL and TC in SFR SCF. Both bits can be
cleared by software when a “0” is written to the bit location. WCOL is reset by hardware when the
SSC transmit data register STB is written with data after a proceeding read operation of the SCF
register. TC is reset by hardware when the receive data register SRB is read the next time after a
proceeding read operation of the SCF register. The interrupt service routine will normally need to
determine whether it was the WCOL or the TC flag which generated the interrupt, and the bit will
need to be cleared by software.
Special Function Register SCF (Address F8H)
Reset Value: XXXX XX00B
Bit
Function
-
Reserved bits for future use. Read by CPU returns undefined values
WCOL
Write Collision Detect
If WCOL is set it indicates that an attempt was made to write to the shift register
STB while a data transfer was in progress and not fully completed. This bit will be
set at the trailing edge of the write signal during the erroneous write attempt. This
bit can be reset in two different ways:
Writing a “0” to the bit (bit access, byte access or read-modify-write access)
Reading the bit or the status register, followed by a write access to STB.
If bit WCEN in the SCIEN register is set, an interrupt request will be generated if
WCOL is set.
TC
Transfer Completed
If TC is set, it indicates that the last transfer has been completed. It is set with the
last sample clock edge of a reception process. This bit can be reset in two different
ways:
Writing a “0” to the bit (bit access, byte access or read-modify-write access) after
the receive buffer register SRB has been read.
Reading the bit or the status register, followed by a read access to SRB.
If bit TCEN in the SCIEN register is set, an interrupt request will be generated if TC
is set.
–
–
–
–
F8H
SCF
Bit No.
7
MSB
LSB
–
–
WCOL
TC
6
5
4
3
2
1
0
