External Bus Interface
C513AO
User’s Manual
4-3
05.99
4.1.2 Timing
Figure 4-1 (a) and (b) illustrate timing of the external bus interface with particular emphasis on the
relationship between the control signals ALE, PSEN, RD, WR and information on Port 0 and Port 2.
Data memory:
In a write cycle, the data byte to be written appears on Port 0 just before WR
is activated and remains there until after WR is deactivated. In a read cycle,
the incoming byte is accepted at Port 0 before the read strobe is deactivated.
Program memory:
Signal PSEN functions as a read strobe.
4.1.3 External Program Memory Access
The external program memory is accessed under either of the following conditions:
• Whenever signal EA of an unprotected device or latched signal EA of a protected device is active
• Whenever the Program Counter (PC) contains a number that is larger than 3FFFH.
Note: For information on unprotected/protected devices, see Section 4.5 ROM/OTP Protection.
For the ROMless version of the device, C513AO-L, to have EA wired low allows program bytes to
be fetched from external memory.
When the CPU is executing out of external program memory, all 8 bits of Port 2 are dedicated to an
output function and may not be used for general-purpose I/O. The contents of the Port 2 SFR,
however, are not affected. During external program memory fetches, Port 2 lines output the high
byte of the Program Counter. During accesses to external data memory, they output either DPH or
the Port 2 SFR (depending on whether the external data memory access is a MOVX @DPTR or a
MOVX @Ri).
Since the C513AO-L has no internal program memory, accesses to program memory are always
external, and Port 2 is dedicated at all times to output of the high-order address byte. This means
that Port 0 and Port 2 of the C513AO-L can never be used as general-purpose I/O. This also applies
to the C513AO-2R or C513AO-2E if they are operated with only an external program memory.
4.2
PSEN, Program Store Enable
The read strobe for external fetches is PSEN. PSEN is not activated for internal fetches. When the
CPU is accessing external program memory, PSEN is activated twice every cycle (except during a
MOVX instruction) whether or not the byte fetched is actually needed for the current instruction.
When PSEN is activated, its timing is not the same as for RD. A complete RD cycle, including
activation and deactivation of ALE and RD, takes twelve oscillator periods. A complete PSEN cycle,
including activation and deactivation of ALE and PSEN, takes six oscillator periods. The execution
sequence for these two types of read cycles is shown in Figure 4-1 (a) and (b).
4.3
Overlapping External Data and Program Memory Spaces
In some applications, it is desirable to execute a program from the same physical memory as that
used for storing data. In the C513AO, the external program and data memory spaces can be
combined by AND-ing PSEN and RD. A positive logic AND of these two signals produces an active
low read strobe that can be used for the combined physical memory. Since the PSEN cycle is faster
than the RD cycle, the external memory needs to be fast enough to adapt to the PSEN cycle.
