IDT 89HPES16T4AG2, Руководство пользователя

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IDT Hot-Plug and Hot-Swap
PES16T4AG2 User Manual 7 - 3 May 23, 2013
Notes The remainder of this section discusses the use of the PES16T4AG2 in an application in which one or
more of the downstream ports are used in an application in which an add-in card may be hot-plugged into a
downstream slot. Associated with each downstream port in the PES16T4AG2 is a hot-plug controller. The
hot-plug controller may be enabled by setting the HPC bit in the PCI Express Slot Capabilities (PCIESCAP)
register associated with that port during configuration (e.g., via serial EEPROM). The PES16T4AG2 allows
sensor inputs and indicator outputs to be located next to the slot or on the plug in module. Regardless of the
physical location, the indicators are controlled by the PES16T4AG2’s downstream port.
Table 7.1 lists the hot-plug inputs and outputs that may be associated with a slot. When enabled during
configuration in the PCIESCAP register, these inputs and outputs are made available to external logic using
an external I/O expander located on the master SMBus interface. When the IO Expander is initialized (i.e.,
the HPC bit in the port’s PCIESCAP register transitions from 0 to 1, or the IOEXPADDR field in the
IOEXPADDR0/1 registers is written to), the hot-plug controller for the corresponding port initiates an SMBus
access to configure the IO Expander and updates the status bits in the PCI Express Slot Status
(PCIESSTS) register. During this initial access, the Presence Detect Changed (PDC) and MRL Sensor
Changed (MRLSC) bits in the PCIESSTS register are not set, since this access is used to determine the
initial state of the IO Expander signals.
The PES16T4AG2 supports presence detect signalling via assertion of the Presence Detect Input signal
in the external I/O Expander module and through “in-band” presence detect. The Presence Detect Control
(PDETECT) field in the Hot-Plug Configuration Control (HPCFGCTL) register may be used to control the
mechanism used for presence detect.
Since the polarity of hot-plug signals has been defined differently in various specifications, each hot plug
signal has a corresponding control bit in the Hot-Plug Configuration Control (HPCFGCTL) that allows the
polarity of that signal to be inverted. Inversion affects the corresponding signal in all ports. When a one is
written to the EIC bit in the PCIESCTL register, then the PxILOCKP signal is pulsed for a length greater
than 100 ms and less than 150 ms (i.e., it transactions from negated to asserted, maintains an asserted
state for 100 to 150 ms, and then transitions back to negated). When the Toggle Electromechanical Inter-
lock Control. (TEMICTL) bit in the HPCFGCTL register is set, writing a one to the EIC bit inverts the state of
the PxILOCKP signal.
When the Replace MRL Status with EMIL Status (RMRLWEMIL) bit is set in the HPCFGCTL register,
the port’s PxMRLN input is used as the electromechanical state input. The state of this input is used as the
state of the electromechanical interlock state obtained by reading the Electromechanical Interlock Status
(EIS) bit in the PCI Express Slot Status (PCIESSTS) register. In this mode, the state of the Manually-oper-
Signal Type Name/Description
PxAPN I Port x
1
Attention Push button Input.
1.
x corresponds to downstream port number (i.e., 1 through 7).
PxPDN I Port x Presence Detect Input.
PxPFN I Port x Power Fault Input.
PxMRLN I Port x Manually-operated Retention Latch (MRL) Input.
PxAIN O Port x Attention Indicator Output.
PxPIN O Port x Power Indicator Output.
PxPEP O Port x Power Enable Output.
PxILOCKP O Port x Electromechanical Interlock.
PxPWRGDN I Port x Power Good Input (asserted when slot power is good).
PxRSTN
2
2.
This signal is a GPIO pin alternate function and is not available as an I/O expander output.
O Port x Reset Output.
Table 7.1 Downstream Port Hot Plug Signals