IDT 89HPES16T4AG2, Руководство пользователя

Страница: 50 / 165

IDT Link Operation
PES16T4AG2 User Manual 3 - 10 May 23, 2013
Notes
Link Status
Associated with each port is a Port Link Up (PxLINKUPN) status output and a Port Activity (PxAC-
TIVEN) status output. These outputs are provided on I/O expander 4. See section I/O Expanders on page
5-7 for the operation of the I/O expander and the mapping of these status outputs to I/O expander pins.
The PxLINKUPN and PxACTIVEN status outputs may be used to provide a visual indication of system
state and activity or for debug. The PxLINKUPN output is asserted when the PCIe data link layer is up (i.e.,
when the LTSSM is in the L0, L0s, L1, or recovery states). When the data link layer is down, this output is
negated. The PxACTIVEN output is asserted whenever any TLP, other than a vendor defined message, is
transmitted or received on the corresponding port’s link. Whenever a PxACTIVEN output is asserted, it
remains asserted for at least 200 ms. Since an I/O expander output may change no more frequently than
once every 40 ms, this translates into five I/O expander update periods.
De-emphasis Negotiation
The PCI Express 2.0 specification requires that components support the following levels of de-
emphasis, depending on the link data rate:
– 2.5 Gbps (Gen1): De-emphasis = -3.5dB
– 5.0 Gbps (Gen2): De-emphasis = -3.5dB or -6.0dB
When operating at 5.0 Gbps, the de-emphasis is selected by programming the Selectable De-emphasis
(SDE) field in the PCI Link Control 2 Register (PCIELCTL2). The chosen de-emphasis for the link is the
result of a negotiation between the components of the link. Both components must operate with the same
de-emphasis across all lanes of the link. During normal operation (i.e, not polling.compliance), de-emphasis
selection is done during the Recovery state. The downstream component of the link (i.e., switch upstream
port or endpoint) advertises its desired de-emphasis by transmission of training sets. The upstream compo-
nent of the link (i.e., switch downstream port or root-complex port) notes its link partner desired de-
emphasis and makes a decision about the de-emphasis to be used in the link.
The PES16T4AG2’s upstream port PHY advertises its desired de-emphasis based on the setting of the
port’s SDE field in the PCIELCTL2 register. The upstream PHY always accepts the link-partners decision
on the de-emphasis to be used in the link. The PES16T4AG2’s downstream ports ignore the link partner’s
desired de-emphasis and always choose the de-emphasis setting in the SDE field of the port’s PCIELCTL2
register.
Low-Swing Transmitter Voltage Mode
The PES16T4AG2 ports support the optional low-swing transmit voltage mode defined in the PCIe 2.0
specification. In this mode, the transmitter’s voltage level is set to approximately half the value of the full-
swing (default) mode. This reduces power consumption in the SerDes. This mode is enabled by setting the
Low-Swing Enable (LSE) bit in the port’s SerDes Control (SERDESCTL) register.
When Low-Swing mode is enabled, the transmitter drive level is reduced and de-emphasis is automati-
cally turned off. Therefore, the Selectable De-emphasis (SDE) and Compliance De-emphasis (CDE) fields
in the PCIELCTL2 register have no effect. In addition, the Current De-emphasis (CDE) field in the
PCIELSTS2 register becomes invalid.
Crosslink
The PES16T4AG2 ports support the optional crosslink capability specified in PCI Express 2.0. Per this
specification, a crosslink is established between two downstream ports or two upstream ports. Crosslink is
enabled when the Crosslink Disable (CLINKDIS) bit in the Phy Link Configuration (PHYLCFG) register is
set to 0x0. The initial value of this field is 0x1 in all switch modes except SWMODE[2:0]=0x4 “Normal switch
mode with crosslink enabled (factory use only).” The user may also clear this bit with a configuration write.