IDT 89HPES16T4AG2, Руководство пользователя

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IDT
PES16T4AG2 User Manual 5 May 23, 2013
Notes November 3, 2008 : In Chapter 1, updated Table 1.2 with additional silicon revisions. Updated the
description for the following fields in Chapter 8: LDIS and LRET in the PCIELCTL register, ULD in the
ALRSTS register, and TLW in the PHYLCFG0 register, and changed the last Reserved field in the
PCIEDCTL2 register from 31:6 to 15:6.
March 30, 2009 : In Chapter 5, deleted old Tables 5.1 and 5.11 dealing with master and slave SMBus
addresses.
May 7, 2009 : In Chapter 3, revised the Lane Reversal section.
July 21, 2009 : In Chapter 3, revised section Dynamic Link Width Reconfiguration Support in the
PES16T4AG2. Also, deleted entire section Software Management of Link Width Upconfiguration and
Downconfiguration.
September 15, 2010 : In Table 1.10, changed Buffer type for PCI Express from CML to PCIe differential
and changed reference clocks to HCSL.
October 26, 2010 : In Chapter 2, revised Clocking section on page 1 to remove reference to REFCLKM.
May 11, 2011 : Deleted all references to DEVNUM field.
September 23, 2011 : Added DDDNC (Disable Downstream Device Number Checking) bit to Switch
Control register in Chapter 8, Configuration Registers.
February 22, 2012 : Added paragraph after Table 5.11 to explain use of DWord addresses.
January 29, 2013 : In Figure 5.8, changed No-ack to Ack between DATALM and DATAUM.
April 30, 2013 : In Table 1.6, changed description for PxxMERGEN pins to pull-up via 92K ohm resistor.
In Table 1.9, changed PxxMERGEN pins from pull-down to pull-up.
May 23, 2013 : In the Features section of Chapter 1, added reference to SECDED ECC under Reliability,
Availability, Serviceability bullet.