IDT 89HPES16T4AG2, Руководство пользователя

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IDT SMBus Interfaces
PES16T4AG2 User Manual 5 - 5 May 23, 2013
Notes The checksum is verified in the following manner. An 8-bit counter is cleared and the 8-bit sum is
computed over the bytes read from the serial EEPROM, including the entire contents of the configuration
done sequence.
1
The correct result should always be 0xFF (i.e., all ones). Checksum checking may be
disabled by setting the Ignore Checksum Errors (ICHECKSUM) bit in the SMBus Control (SMBUSCTL)
register.
If an error is detected during loading of the serial EEPROM, then loading of the serial EEPROM is
aborted and the RSTHALT bit is set in the SWCTL register. This allows debugging of the error condition via
the slave SMBus interface but prevents normal system operation with a potentially incorrectly initialized
device. Error information is recorded in the SMBUSSTS register.
Once serial EEPROM initialization completes, or when an error is detected, the EEPROM Done
(EEPROMDONE) bit is set in the SMBus Status (SMBUSSTS) register. A summary of possible errors
during serial EEPROM initialization and specific action taken when detected is summarized in Table 5.2.
Programming the Serial EEPROM
The serial EEPROM may be programmed prior to board assembly or in-system via the slave SMBus
interface or a PCIe root. Programming the serial EEPROM via the slave SMBus is described in section
Serial EEPROM Read or Write Operation on page 5-16.
A PCIe root may read and write the serial EEPROM by performing configuration read and write transac-
tions to the Serial EEPROM Interface (EEPROMINTF) register. To read a byte from the serial EEPROM, the
root should configure the Address (ADDR) field in the EEPROMINTF register with the byte address of the
serial EEPROM location to be read and the Operation (OP) field to “read.” The Busy (BUSY) bit should then
be checked. If the EEPROM is not busy, then the read operation may be initiated by performing a write to
the Data (DATA) field. When the serial EEPROM read operation completes, the Done (DONE) bit in the
EEPROMINTF register is set and the busy bit is cleared. When this occurs, the DATA field contains the byte
data of the value read from the serial EEPROM.
To write a byte to the serial EEPROM, the root should configure the ADDR field with the byte address of
the serial EEPROM location to be written and set the OP field to “write.” If the serial EEPROM is not busy
(i.e., the BUSY bit is cleared), then the write operation may be initiated by writing the value to be written to
the DATA field. When the write operation completes, the DONE bit is set and the busy bit is cleared. Initi-
ating a serial EEPROM read or write operation when the BUSY bit is set produces undefined results.
1.
This includes the checksum byte as well as the byte that contains the type and reserved field.
Error Action Taken
Configuration Done Sequence checksum
mismatch with that computed by the
PES16T4AG2 - Set RSTHALT bit in SWCTL register
- ICSERR bit is set in the SMBUSSTS register
- Abort initialization, set DONE bit in the SMBUSSTS register
Invalid configuration block type
(only invalid type is 0x2) - Set RSTHALT bit in SWCTL register
- ICSERR bit is set in the SMBUSSTS register
- Abort initialization, set DONE bit in the SMBUSSTS register
An unexpected NACK is observed during a
master SMBus transaction - Set RSTHALT bit in SWCTL register
- NAERR bit is set in the SMBUSSTS register
- Abort initialization, set DONE bit in the SMBUSSTS register
Master SMBus interface loses 16 consecu-
tive arbitration attempts - Set RSTHALT bit in SWCTL register
- LAERR bit is set in the SMBUSSTS register
- Abort initialization, set DONE bit in the SMBUSSTS register
A misplaced START or STOP condition is
detected by the master SMBus interface - Set RSTHALT bit in SWCTL register
- OTHERERR bit is set in the SMBUSSTS register
- Abort initialization, set DONE bit in the SMBUSSTS register
Table 5.2 Serial EEPROM Initialization Errors