IDT 89HPES16T4AG2, Руководство пользователя

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IDT Clocking, Reset and Initialization
PES16T4AG2 User Manual 2 - 6 May 23, 2013
Notes When an Upstream Secondary Bus Reset occurs, the following sequence is executed.
1. Each downstream port whose link is up propagates the reset by transmitting TS1 ordered sets with
the hot reset bit set.
2. All registers fields in all registers associated with downstream ports, except those denoted as “sticky”
or Read and Write when Unlocked (i.e, RWL), are reset to their initial value. The value of fields
denoted as “sticky” or RWL is unaffected by an Upstream Secondary Bus Reset.
3. All TLPs received from downstream ports and queued in the PES16T4AG2 are discarded.
4. Logic in the stack, application layer, and switch core associated with the downstream ports are
gracefully reset.
5. Wait for software to clear the Secondary Bus Reset (SRESET) bit in the upstream port’s Bridge
Control Register (BCTL).
6. Normal downstream port operation begins.
The operation of the upstream port is unaffected by a secondary bus reset. The link remains up and
Type 0 configuration read and write transactions that target the upstream port complete normally. During an
Upstream Secondary Bus Reset, all TLPs destined to the secondary side of the upstream port’s PCI-to-PCI
bridge are treated in an undefined manner. The user should ensure no TLPs are sent to the secondary side
of the upstream port’s PCI-to-PCI bridge until the SRESET bit in the BCTL register is cleared.
The operation of the slave SMBus interface is unaffected by an Upstream Secondary Bus Reset. Using
the slave SMBus to access a register that is reset by an Upstream Secondary Bus Reset causes the
register’s default value to be returned on a read and written data to be ignored on writes.
Downstream Secondary Bus Reset
A Downstream Secondary Bus Reset may be initiated by the following condition:
– A one is written to the Secondary Bus Reset (SRESET) bit in a downstream port’s (i.e., port 0)
Bridge Control Register (BCTL).
When a Downstream Secondary Bus Reset occurs, the following sequence is executed.
1. If the corresponding downstream port’s link is up, TS1 ordered sets with the hot reset bit set are
transmitted.
2. All TLPs received from corresponding downstream port and queued in the PES16T4AG2 are
discarded.
3. Wait for software to clear the Secondary Bus Reset (SRESET) bit in the upstream port’s Bridge
Control Register (BCTL).
4. Normal downstream port operation begins.
The operation of the upstream port is unaffected by a Downstream Secondary Bus Reset. The operation
of other downstream ports is unaffected by a Downstream Secondary Bus Reset. During a Downstream
Secondary Bus Reset, Type 0 configuration read and write transactions that target the downstream port
complete normally. During a Downstream Secondary Bus Reset, all TLPs destined to the secondary side of
the downstream port’s PCI-to-PCI bridge are treated as unsupported requests. The operation of the slave
SMBus interface is unaffected by a Downstream Secondary Bus Reset.
Downstream Port Reset Outputs
Individual downstream port reset outputs (P1RSTN, P2RSTN, P3RSTN, P4RSTN, P5RSTN, P6RSTN,
and P7RSTN) are provided as GPIO pin alternate functions. Following a Fundamental Reset, all of the
GPIO pins default to GPIO inputs. Therefore, the downstream port resets are tri-stated. A system designer
should use a pull-down on these signals if they are used as reset outputs.
The PES16T4AG2 ensures through hardware that the minimum PxRSTN assertion pulse width is no
less than 200 µs.