IDT 89HPES16T4AG2, Руководство пользователя

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IDT SMBus Interfaces
PES16T4AG2 User Manual 5 - 8 May 23, 2013
Notes The following I/O expander configuration sequence is issued by the PES16T4AG2 to I/O expander four
(i.e., the one that contains link up and link activity status).
– Write link up status for all ports to the lower eight I/O expander pins (i.e., I/O-0.0 through I/O-0.7)
to I/O expander register 2.
– Write link activity status for all ports to the upper eight I/O expander pins (i.e., I/O-1.0 through I/O-
1.7) to I/O expander register 3.
– write value 0x0 to I/O expander register 4 (no inversion in IO-0)
– write value 0x0 to I/O expander register 5 (no inversion in IO-1)
– Write the configuration value to select all outputs in the lower eight I/O expander bits (i.e., I/O-0.0
through I/O-0.7) to I/O expander register 6.
– Write the configuration value to select all outputs in the upper eight I/O expander bits (i.e., I/O-1.0
through I/O-1.7) to I/O expander register 7.
While the I/O expander is enabled, the PES16T4AG2 maintains the I/O bus expander signals and the
PES16T4AG2 internal view of the hot-plug signals in a consistent state. This means that whenever that I/O
bus expander state and the PES16T4AG2 internal view of the signal state differs, an SMBus transaction is
initiated by the PES16T4AG2 to resolve the state conflict. An example of an event that may lead to a state
conflict is a hot reset. When a hot reset occurs, one or more hot-plug register control fields may be re-initial-
ized to its default value. When this occurs, the internal PES16T4AG2 state of the hot-plug signals is in
conflict with the state of I/O expander hot-plug output signals. In such a situation, the PES16T4AG2 will
initiate an SMBus transaction to modify the state of the I/O expander hot-plug outputs
The PES16T4AG2 has one combined I/O expander interrupt input, labeled IOEXPINTN0, which is an
alternate function of GPIO[2]. Associated with each I/O expander is an open drain interrupt output that is
asserted when an I/O expander input pin changes state. The open drain I/O expander interrupt output of all
I/O expanders should be tied together on the board and connected to GPIO[2]. Whenever IOEXPINTN0 is
asserted, the PES16T4AG2 reads the state of all I/O expanders.
For compatibility with legacy Gen. 1 PCIe switches, the PES16T4AG2 supports individual I/O expander
interrupt inputs (i.e., IOEXPINTN[3:0]) as GPIO alternate functions. New designs should use the combined
I/O expander interrupt input.
In legacy applications, each interrupt output from an I/O expander should be connected to the corre-
sponding PES16T4AG2 I/O expander interrupt input. For Legacy Gen 1 switch compatibility, the
PES16T4AG2 internally logically “ORs” the legacy I/O expander interrupts on GPIO alternate functions and
presents a single combined interrupt value to internal logic in the same manner as the external combined I/
O expander interrupt input. Therefore, the PES16T4AG2 behaves in the same manner in applications that
use a single external combined I/O expander interrupt input as it does in applications that use legacy indi-
vidual I/O expander interrupt inputs. In both cases, the assertion of any I/O expander interrupt results in a
status read of all I/O expanders. Since the PES16T4AG2 I/O expander interrupt input(s) are GPIO alternate
functions, the corresponding GPIO(s) should be initialized during configuration to operate in alternate func-
tion mode. See Chapter 4, General Purpose I/O.
Whenever the PES16T4AG2 needs to change the state of an I/O expander signal output, a master
SMBus transaction is initiated to update the state of the I/O expander. This write operation causes the
corresponding I/O expander to change the state of its output(s). The PES16T4AG2 will not update the state
of an I/O expander output more frequently than once every 40 milliseconds. This 40 millisecond time
interval is referred to as the I/O expander update period.
Whenever an input to the I/O expander changes state from the value previously read, the interrupt
output of the I/O expander is asserted. This causes the PES16T4AG2 to issue a master SMBus transaction
to read the updated state of all I/O expander inputs. In legacy Gen1 devices, the PCIe switch would only
read the state of the I/O expander that asserted the interrupt. Whenever any I/O expander interrupt is
asserted, the PES16T4AG2 reads and updates the state of all I/O expander inputs.