7: B
ASIC
I
NSTRUCTIONS
FC5A M
ICRO
S
MART
U
SER
’
S
M
ANUAL
FC9Y-B1268
7-5
AND and ANDN (And Not)
The AND instruction is used for programming a NO contact in series. The ANDN instruction is used for programming a NC
contact in series. The AND or ANDN instruction is entered after the first set of contacts.
Ladder Diagram
I0
Instruction
Data
LOD
AND
OUT
LOD
ANDN
OUT
I0
I1
Q0
I0
I1
Q1
Program List
I1
I1
I0
I0
ON
OFF
I1
ON
OFF
Q0
ON
OFF
Q1
ON
OFF
Timing Chart
When both inputs I0 and I1 are on, output Q0 is on. When either input I0 or I1 is off, output Q0 is off.
When input I0 is on and input I1 is off, output Q1 is on. When either input I0 is off or input I1 is on, output Q1 is off.
Valid Devices
The valid device range depends on the CPU module type. For details, see pages 6-1 and 6-2.
Data registers can be used as bit devices with the data register number and the bit position separated by
a period.
Instruction
I
Q
M
T
C
R
D
AND
ANDN
0-627
0-627
0-2557
8000-8317
0-255
0-255
0-255
0.0-49999.15
Q0
Q1
OR and ORN (Or Not)
The OR instruction is used for programming a NO contact in parallel. The ORN instruction is used for programming a NC
contact in parallel. The OR or ORN instruction is entered after the first set of contacts.
Ladder Diagram
I0
I0
I0
ON
OFF
I1
ON
OFF
Q0
ON
OFF
Q1
ON
OFF
Timing Chart
When either input I0 or I1 is on, output Q0 is on. When both inputs I0 and I1 are off, output Q0 is off.
When either input I0 is on or input I1 is off, output Q1 is on. When input I0 is off and input I1 is on, output Q1 is off.
I1
I1
Instruction
Data
LOD
OR
OUT
LOD
ORN
OUT
I0
I1
Q0
I0
I1
Q1
Program List
Valid Devices
The valid device range depends on the CPU module type. For details, see pages 6-1 and 6-2.
Data registers can be used as bit devices with the data register number and the bit position separated by
a period.
Instruction
I
Q
M
T
C
R
D
OR
ORN
0-627
0-627
0-2557
8000-8317
0-255
0-255
0-255
0.0-49999.15
Q0
Q1
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