IDEC MicroSmart pentra FC5A-C10R2, Руководство пользователя

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5: S
PECIAL
F
UNCTIONS
5-46 FC5A M
ICRO
S
MART
U
SER
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S
M
ANUAL
FC9Y-B1268
32-bit Data Storage Setting
When the double-word, long, or float data type is selected for the source or destination device, the data is loaded from
or stored to two consecutive data registers. The order of two devices can be selected from the following two settings in
the Function Area Settings.
This setting can be used on CPU modules with system program version 110 or higher.
Setting Description
From Upper Word
When a data register, timer, or counter is used as a double-word device, the high-word data is
loaded from or stored to the first device selected. The low-word data is loaded from or stored to
the subsequent device.
This is identical with the 32-bit data storage of OpenNet Controller and FC4A MicroSmart, and is
the default setting of the FC5A MicroSmart.
From Lower Word
When a data register, timer, or counter is used as a double-word device, the low-word data is
loaded from or stored to the first device selected. The high-word data is loaded from or stored to
the subsequent device.
This is identical with the 32-bit data storage of IDEC FA Series PLCs.
Devices
When the devices listed below are used as a double-word device, two consecutive devices are processed according to the
32-bit data storage settings.
Device Device Address
Data Register D0 - D1999
Expansion Data Register D2000 - D7999
Special Data Register D8000 - D8499
Extra Data Register D10000 - D49999
Timer T0 - T255
Counter C0 - C255
Instructions
The 32-bit data storage setting has the effect on the following instructions: CNTD, CDPD, CUDD, MOV, MOVN, IMOV,
IMOVN, NSET, NRS, TCCST, CMP=, CMP<>, CMP<, CMP>, CMP<=, CMP>=, ICMP>=, LC=, LC<>, LC<, LC>, LC<=, LC>=, ADD,
SUB, MUL, DIV, ROOT, ANDW, ORW, XORW, BCDLS, ROTL, ROTR, HTOB, BTOH, BTOA, ATOB, CVDT, AVRG, PULS, PWM,
RAMP, RAD, DEG, SIN, COS, TAN, ASIN, ACOS, ATAN, LOGE, LOG10, EXP, and POW.
Data Register Allocation
The 32-bit data storage setting has the effect on data register allocation of the following functions: PULS, PWM, and
RAMP instructions, frequency measurement, and high-speed counter. All of these functions can be used on the slim type
CPU modules only.
Control Registers for PULS or PWM Instruction
Device Address Description From Upper Word From Lower Word
S1+3
Preset Value 1 to 100,000,000 (05F5E100h)
High Word Low Word
S1+4 Low Word High Word
S1+5
Current Value 1 to 100,000,000 (05F5E100h)
(PULS1, PULS3, PWM1, and PWM3 only)
High Word Low Word
S1+6 Low Word High Word
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