IBM z13s, Техническое руководство

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Chapter 3. Central processor complex system design
111
The assignment rules follow this order:
򐂰 Spare: On CPC drawer 1, no spare is assigned on the high PU SCM. In the Model N10, no
spares are assigned.
򐂰
IFP: If only CPC drawer 1 is present (Model N10, one CPC drawer machine, or Model
N20, one CPC drawer machine), the IFP is assigned to the high PU SCM. If drawer 0 is
present on the machine (Model N20, two CPC drawer machine), then the IFP is in CPC
drawer 0 high PU SCM.
򐂰 SAPs: Spread across CPC drawers and high PU SCMs. CPC drawer 1 has two standard
SAPs. Start with the highest PU SCM high core, then the next highest PU SCM high core.
This configuration prevents all the SAPs from being assigned on one PU SCM.
򐂰 IFLs and ICFs: Assign IFLs and ICFs to cores on SCMs in higher CPC drawers working
downward.
򐂰 CPs and zIIPs: Assign CPs and zIIPs to cores on SCMs in lower CPC drawers working
upward.
These rules are intended to isolate, as much as possible, on different CPC drawers and even
on different PU chips, processors that are used by different operating systems. This
configuration ensures that different operating systems do not use the same shared caches.
For example, CPs and zIIPs are all used by z/OS, and can benefit by using the same shared
caches. However, IFLs are used by z/VM and Linux, and ICFs are used by CFCC. Therefore,
for performance reasons, the assignment rules prevent them from sharing L3 and L4 caches
with z/OS processors.
This initial PU assignment, which is done at POR, can be dynamically rearranged by an LPAR
by swapping an active core with a core in a different PU chip in a different CPC drawer or
node to improve system performance. For more information, see “LPAR dynamic PU
reassignment” on page 123.
When an extra CPC drawer is added after a POR, processor resources are spread across all
available CPC drawers. The processor unit assignment rules consider the newly installed
CPC drawer only after the next POR.
3.5.10 Sparing rules
On a z13s Model N20 system, two PUs are reserved as spares. There are no spare PUs
reserved on a z13s Model N10. The reserved spares are available to replace any
characterized PUs, whether they are CP, IFL, ICF, zIIP, SAP, or IFP.
Systems with a failed PU for which no spare is available will
call home
for a replacement. A
system with a failed PU that is spared and requires an SCM to be replaced (referred to as a
pending repair
) can still be upgraded when sufficient PUs are available.
Transparent CP, IFL, ICF, zIIP, SAP, and IFP sparing
Depending on the model, sparing of CP, IFL, ICF, zIIP, SAP, and IFP is transparent and does
not require operating system or operator intervention.
With
transparent sparing
, the status of the application that was running on the failed
processor is preserved. The application continues processing on a newly assigned CP, IFL,
ICF, zIIP, SAP, or IFP (allocated to one of the spare PUs) without client intervention.
Note: The addition of a second CPC drawer is disruptive.