IBM z13s, Техническое руководство

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Chapter 3. Central processor complex system design
87
Compared to zBC12, the z13s cache design has much larger cache level sizes. z13s servers
have more affinity between the memory of a partition, the L4 cache in the SC SCM, and the
cores in the PU SCMs of a node. The access time of the private cache usually occurs in one
cycle. The z13 cache level structure is focused on keeping more data closer to the PU. This
design can improve system performance on many production workloads.
HiperDispatch
To help avoid latency in a high-frequency processor design, such as z13s servers, prevent
PR/SM and the dispatcher from scheduling and dispatching a workload on any processor
available. Also, keep the workload in as small a portion of the system as possible. The
cooperation between z/OS and PR/SM is bundled in a function called
HiperDispatch
.
HiperDispatch uses the z13s cache topology, which has reduced cross-node “help” and better
locality for multi-task address spaces.
PR/SM can use dynamic PU reassignment to move processors (CPs, zIIPs, IFLs, ICFs,
SAPs, and spares) to a different chip, node, and drawer to improve the reuse of shared
caches by processors of the same partition. It can use dynamic memory relocation (DMR) to
move a running partition’s memory to different physical memory to improve the affinity and
reduce the distance between the memory of a partition and the processors of the partition.
For more information about HiperDispatch, see 3.7, “Logical partitioning” on page 116.
3.3.2 CPC drawer interconnect topology
CPC drawers are interconnected in a point-to-point topology, allowing a node in a CPC
drawer to communicate with every other node (four nodes in two CPC drawers). Data transfer
does not always have to go through another node or CPC drawer (cache) to address the
requested data or control information.
Figure 3-4 shows the z13s CPC drawer communication structure (intra- and inter- drawers).
Figure 3-4 z13s CPC drawer communication topology
Intra-node interface
X-BUS
Intra-node interface
X-BUS
PCIe Memory
PU
GX++
Memory
PU
GX++ PSI
PCIe
SC
A-BUS
PCIe
PU
GX++
Memory
PU
GX++
PSI
PCIe
SC
A-BUS
Node 1
Node 0
CPC Drawer
To other drawer
(SMP connector)
To other drawer
(SMP connector)
Memory
Inter-node
interface
S-BUS