IBM z13s, Техническое руководство

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IBM z13s Technical Guide
Figure 3-6 shows two threads (A and B) running on the same processor core on different
pipeline stages, sharing the core resources.
Figure 3-6 Two threads running simultaneously on the same processor core
The use of SMT provides more efficient use of the processors’ resources and helps address
memory latency, resulting in overall throughput gains. The active thread shares core
resources in space, such as data and instruction caches, TLBs, branch history tables, and, in
time, pipeline slots, execution units, and address translators.
Although SMT increases the processing capacity, the performance in some cases might be
superior if you use a single thread. Enhanced hardware monitoring supports measurement
through CPU Measurement Facility (CPUMF) for thread usage and capacity.
For workloads that need maximum thread speed, the partition’s SMT mode can be turned off.
For workloads that need more throughput to decrease the dispatch queue size, the partition’s
SMT mode can be turned on.
The SMT exploitation is functionally transparent to middleware and applications, and no
changes are required to run them in an SMT-enabled partition.
3.4.2 Single-instruction multiple-data
The z13s superscalar processor has 32 vector registers and an instruction set architecture
that includes a subset of 139 new instructions, known as SIMD, added to improve the
efficiency of complex mathematical models and vector processing. These new instructions
allow a larger number of operands to be processed with a single instruction. The SIMD
instructions use the superscalar core to process operands in parallel.
SIMD provides the next phase of enhancements of z Systems analytics capability. The set of
SIMD instructions are a type of data parallel computing and vector processing that can
decrease the amount of code and accelerate code that handles integer, string, character, and
floating point data types. The SIMD instructions improve performance of complex
mathematical models and allow integration of business transactions and analytic workloads
on z Systems.
A
/
B
A
B
B
Load/Store (L1 Cache)
A A B
Execution Units (FXU/FPU)
instructions
A B A A
B A
A
B
Shared Cache
A
B
A A
B A
B A
Cache
Thread-A
Thread-B
Use of Pipeline Stages in SMT2
Both threads
Stage idle