IBM z13s, Техническое руководство

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IBM z13s Technical Guide
SUSE) can use Flash Express for temporary storage. Recent enhancements of Flash
Express include 2 GB page support and dynamic reconfiguration for Flash Express.
For more information, see Appendix H, “Flash Express” on page 529.
zEDC Express
zEDC Express
, an optional feature that is available to z13, z13s, zEC12, and zBC12 servers,
provides hardware-based acceleration for data compression and decompression with lower
CPU consumption than the previous compression technology on z Systems.
Use of the zEDC Express feature by the z/OS V2R1or later zEnterprise Data Compression
acceleration capability delivers an integrated solution to help reduce CPU consumption,
optimize performance of compression-related tasks, and enable more efficient use of storage
resources. It also provides a lower cost of computing and helps to optimize the cross-platform
exchange of data.
One to eight features can be installed on the system. There is one PCIe adapter/compression
coprocessor per feature, which implements compression as defined by RFC1951 (DEFLATE).
A zEDC Express feature can be shared by up to 15 LPARs.
See the IBM System z Batch Network Analyzer 1.4.2 tool, which reports on potential zEDC
usage for QSAM/BSAM data sets:
http://www.ibm.com/support/techdocs/atsmastr.nsf/WebIndex/PRS5132
For more information, see Appendix J, “IBM zEnterprise Data Compression Express” on
page 551.
1.3.9 Reliability, availability, and serviceability
The z13 and z13s RAS strategy employs a building-block approach, which is developed to
meet the client's stringent requirements for achieving continuous reliable operation. Those
building blocks are error prevention, error detection, recovery, problem determination, service
structure, change management, measurement, and analysis.
The initial focus is on preventing failures from occurring. This goal is accomplished by using
Hi-Rel
(highest reliability) components that use screening, sorting, burn-in, and run-in, and by
taking advantage of technology integration. For LICCand hardware design, failures are
reduced through rigorous design rules; design walk-through; peer reviews; element,
subsystem, and system simulation; and extensive engineering and manufacturing testing.
The RAS strategy is focused on a recovery design to mask errors and make them transparent
to client operations. An extensive hardware recovery design is implemented to detect and
correct memory array faults. In cases where transparency cannot be achieved, you can
restart the server with the maximum capacity possible.
z13s servers include the following RAS improvements, among others:
򐂰 Cables for SMP fabric
򐂰 CP and SC SCMs are FRUs
򐂰 Point of load (POL) replaces the Voltage Transformation Module, and is a FRU
򐂰 z13s servers have both raised floor and non-raised-floor options
򐂰 The redundant oscillators are isolated on their own backplane
򐂰 The CPC drawer is a FRU (empty)
򐂰 A built-in Time Domain Reflectometry (TDR) isolates failures
򐂰 CPC drawer level degrade