IBM z13s, Техническое руководство

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IBM z13s Technical Guide
1.3.4 CPC drawer
Up to two CPC drawers (minimum one) can be installed in the z13s frame. Each CPC drawer
houses the SCMs, memory, and fanouts. The CPC drawer supports up to 8 PCIe fanouts and
4 IFB fanouts for I/O and coupling connectivity.
In the N20 two CPC drawer model, CPC drawers are connected through cables that are also
field-replaceable units (FRUs) and can be replaced concurrently, unlike the disruptive bus
repair on the zBC12.
SCM technology
z13s servers are built on the superscalar microprocessor architecture of its predecessor, and
provides several enhancements over the zBC12. Each CPC drawer is physically divided into
two nodes. Each node has three SCMs: Two PU SCMs, and one storage control (SC) SCM.
A fully configured CPC drawer has four PU SCMs and two SC SCMs. The PU SCM has eight
cores (six or seven active), which can be characterized as CPs, IFLs, ICFs, zIIPs, SAPs, or
IFPs. Two CPC drawers sizes are offered: 10 cores (N10) and 20 cores (N20).
On the N20, the PU configuration includes two designated spare PUs. The N10 has no
dedicated spares. Two standard SAPs are installed with the N10 Model and up to three SAPs
for the N20 Model. In addition, one PU is used as an IFP and is not available for client use.
The remaining PUs can be characterized as CPs, IFL processors, zIIPs, ICF processors, or
extra SAPs. For more information, see 3.3, “CPC drawer design” on page 84 and 3.4,
“Processor unit design” on page 88.
Processor features
The processor chip runs at 4.3 GHz. Depending on the model, either 13 PUs (N10) or 26 PUs
(N20) are available. Each core on the PU chip includes an enhanced dedicated coprocessor
for data compression and cryptographic functions, which are known as the Central Processor
Assist for Cryptographic Function (CPACF)
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Hardware data compression can play a significant role in improving performance and saving
costs over performing compression in software (thus consuming CPU cycles). In addition, the
zEDC Express feature offers more performance and savings. It is designed to provide
compression capabilities that compliment those provided by the data compression on the
coprocessor.
The micro-architecture of the core has been enhanced to increase parallelism and improve
pipeline efficiency. The core has a new branch prediction and instruction fetch front end to
support simultaneous multithreading in a single core and to improve the branch prediction
throughput, a wider instruction decode (six instructions per cycle), and 10 arithmetic logical
execution units that offer double instruction bandwidth over the zBC12.
Each core has two hardware decimal floating point units that are designed according to a
standardized, open algorithm. Two on-core hardware decimal floating point units meet the
requirements of today’s business and user applications, and provide greater floating point
execution throughput with improved performance and precision.
Important: Concurrent drawer repair, concurrent drawer add, and concurrent memory add
are not available on z13s servers.
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No charge feature code (FC) 3863 must be ordered to enable CPACF