IBM z13s, Техническое руководство

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Chapter 7. Software support
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Structure size requirements for real memory get larger at initial allocation time to
accommodate more control objects that are needed to use flash memory.
The CFSIZER structure recommendations consider these additional requirements, both for
sizing the structure’s flash usage and for the related real memory considerations.
The following are the minimum CFCC Flash Express use requirements:
򐂰 CFCC Level 19 support or later
򐂰 z/OS support for z/OS V1R13 with PTFs and z/OS V2R1 or later with PTFs
WebSphere MQ Version 7 is required.
7.8.3 CFCC Coupling Thin Interrupts
The Coupling Thin Interrupts enhancement, which is delivered with CFCC 19, improves the
performance of a Coupling Facility partition and the dispatching of z/OS LPARs awaiting the
arrival of returned asynchronous CF requests, when used in a shared engine environment.
7.9 Simultaneous multithreading
The z13s can run up two threads simultaneously in the same processor, dynamically sharing
resources of the core such as cache, TLB, and execution resources. It provides better
utilization of the cores and more processing capacity. This function is known as SMT, and is
available only in zIIP and IFL cores. For more information about SMT, see 3.4.1,
“Simultaneous multithreading” on page 89.
The z/OS and the z/VM have SMT support if the support is enabled by PTFs. z/OS 2.2
supports the operation of zIIP processors in SMT mode.
The following APARs must be applied to z/OS V2R1 to use SMT
5
:
򐂰
OA43366 (BCP)
򐂰
OA43622 (WLM)
򐂰
OA44439 (XCF)
The use of SMT on z/OS V2R1 and later requires enabling HiperDispatch, and defining the
processor view (
PROCVIEW
) control statement in the LOADxx parmlib member and the
MT_ZIIP_MODE
parameter in the IEAOPTxx parmlib member.
The PROCVIEW statement is defined for the life of IPL, and can have the following values:
򐂰 CORE : This value specifies that z/OS should configure a processor view of core, where a
core can have one or more threads. The number of threads is limited by z13s to two. If the
underlying hardware does not support SMT, a core is limited to one thread.
򐂰 CPU
: This value is the default. It specifies that z/OS should configure a traditional processor
view of CPU and not use SMT.
򐂰 CORE,CPU_OK : This value specifies that z/OS should configure a processor view of core, as
with the CORE value, but the CPU parameter is accepted as an alias for applicable
commands.
Important: Flash memory is
not
pre-assigned to structures at allocation time.
5
SMT is only available for zIIP workload.