IBM p5 590, Системный справочник

Страница: 53 / 316

Chapter 2. Hardware architecture
31
Figure 2-7 on page 32 provides a logical view of the CEC components. It shows
a system populated with two MCMs, eight dual core POWER5 processors, eight
L3 cache modules, eight GX+ adapter card slots, the memory subsystem, and
dual processor clock.
The CEC houses up to four processor books. Each processor book consists of
two MCMs, memory, and GX+ ports (for Remote I/O or for the High Performance
Switch
4
). A single MCM has exactly four dual-core POWER5 chips and their
Level 3 cache memory (4 x 36 MB). A p5-595 supports maximum of eight MCMs
and is 64-way (4 x 2 x 8).
The p5-595 supports a maximum configuration of four processor books, which
allows for 64-way processing.
The p5-590 is packaged in the same physical structure as the p5-595. However,
the p5-590 supports a maximum of two processor books, which allows for
32-way processing.
The enhanced GX+ high frequency processor bus drives synchronous memory
Interface (SMI) memory buffer chips and interfaces with a 36 MB L3 cache
controller. The processor bus provides eight bus adapter slots to interface with
two types of bus technologies:
򐂰
I/O bus bridges
򐂰 CEC interconnect bridge to support clustered system configurations. The
p5-590 does not support clustered configurations.
The main service processor function is located in the CEC. The service
processor subsystem runs an independent operating system and directly drives
Ethernet ports to connect the external IBM l Hardware Management Console.
The service processor unit is not specifically represented in the CEC logic
diagram, Figure 2-7 on page 32. The service processor is explained in more
detail in Chapter 7, “Service processor” on page 169.
There are 16 memory card slots available for the p5-595 and p5-590. For
detailed information about memory, refer to 2.3.2, “Memory placement rules” on
page 28.
4
A Statement of Direction has been announced for this product for the first half of 2005.