IBM p5 590, Системный справочник

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Chapter 6. Reliability, availability, and serviceability
153
CPU dynamic deconfiguration relies on the service processor’s ability to use
FFDC generated recoverable-error information and to notify the AIX 5L operating
system when the CPU reaches its predefined error limit. AIX 5L will then
drain
the run-queue for that CPU, redistribute the work to the remaining CPUs,
deallocate the offending CPU, and continue normal operation, although
potentially at a lower level of system performance. While AIX Version 4.3.3
precluded the ability for a SMP server to revert to a uniprocessor (for example, a
2-way to a 1-way configuration), this limitation was lifted with AIX 5L Version 5.1.
AIX 5L Version 5.2 support for dynamic logical partitioning (dynamic LPAR)
allowed additional system availability improvements. An IBM
Sserver
p5 server
that includes an inactive CPU (an unused CPU included in a Capacity Upgrade
on Demand (CUoD) system configuration) can be configured for CPU
hot-sparing. In this case, as a system option, the inactive CPU can automatically
be used to
back-fill
for the deallocated bad processor. In most cases, this
operation is transparent to the system administrator and to end users. The spare
CPU is logically moved to the target system partition or shared processor pool,
AIX 5L and Linux moves the workload, and the failing processor is deallocated.
The server continues normal operation with full function and full performance.
The system will generate an error message for inclusion in the error logs calling
for deferred maintenance of the faulty component.
Refer to Chapter 4, “Capacity on Demand” on page 85 for more detail about
CoD.
POWER5 technology and AIX 5L Version 5.3 and Linux introduce new levels of
virtualization, supporting Micro-Partitioning technology, allowing individual
processors to run as many as ten copies of the operating system. These new
capabilities allow improvements in the CPU hot-spare strategy. POWER5 chips
will support both dedicated processor logical partitions and shared processor
dynamic LPAR. Dedicated processor partitions, supporting AIX Version 5.2 and
V5.3, operate like POWER4 processor-based system logical partitions. In a
dedicated processor LPAR, one or more physical CPUs are assigned to the
partition.
In shared processor partitions, supported by AIX 5L Version 5.3, a shared
processor pool of physical processors is defined. This shared processor pool
consists of one or more physical processors. In this environment, partitions are
defined to include virtual processor and processor entitlements. Entitlements can
be considered to be performance equivalents.
In dedicated POWER5 processor partitions, CPU sparing is transparent to the
operating system. When a CPU reaches its error threshold, the active service
processor notifies the POWER Hypervisor to initiate a deallocation event.